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| document no. u15905ej2v1ud00 (2nd edition) date published august 2005 n cp(k) printed in japan ? user?s manual v850es/sa2, v850es/sa3 32-bit single-chip microcontrollers hardware v850es/sa2: v850es/sa3: pd703200 pd703204 pd703200y pd703204y pd703201 pd70f3204 pd703201y pd70f3204y pd70f3201 pd70f3201y
user?s manual u15905ej2v1ud 2 [memo] user?s manual u15905ej2v1ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 user?s manual u15905ej2v1ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of july, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": user?s manual u15905ej2v1ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: user?s manual u15905ej2v1ud 6 preface readers this manual is intended for users who wish to understand the functions of the v850es/sa2 ( pd703200, 703200y, 703201, 703201y , 70f3201, 70f3201y) and v850es/sa3 ( pd703204, 703204y, 70f3204, 70f3204y ) and design application systems using these products. purpose this manual is intended to give users an understanding of the har dware functions of the v850es/sa2 and v850es/sa3 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to learn the detailed functions of a r egister whose register name is known refer to appendix a register index . to understand the details of an instruction function refer to the v850es architecture user?s manual available separately. register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defi ned as a reserved word in the device file. to understand the overall functions of the v850es/sa2 and v850es/sa3 read this manual according to the contents . to know the electrical specificat ions of the v850es/sa2 and v850es/sa3 refer to chapter 22 electrical specifications . the mask shows the major revised points. user?s manual u15905ej2v1ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresse s on the top and lower addresses on the bottom note: footnote for item marked with note in the text caution: information requiring particular attention remark: supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/sa2 and v850es/sa3 document name document no. v850es architecture user?s manual u15943e v850es/sa2, v850es/sa3 hardware user?s manual this manual v850es/sa2, v850es/sa3 application note u16764e documents related to development tools document name document no. ie-v850es-g1 (in-circuit emulator) u16313e ie-703204-g1-em1 (in-circuit em ulator option board) u16622e operation u16053e c language u16054e ca850 c compiler package ver. 2.50 assembly language u16042e pm plus ver. 5.10 u16569e id850 integrated debugger ver. 2.50 operation u16217e basics u13430e installation u13410e rx850 real-time os ver. 3.13 or later technical u13431e basics u13773e installation u13774e rx850 pro real-time os ver. 3.15 technical u13772e rd850 task debugger ver. 3.01 u13737e rd850 pro task debugger ver. 3.01 u13916e az850 system performance analyzer ver. 3.20 u14410e pg-fp4 flash memory programmer u15260e user?s manual u15905ej2v1ud 8 contents chapter 1 introduction ...................................................................................................... ............16 1.1 overview....................................................................................................................... .............16 1.2 features....................................................................................................................... ..............17 1.3 application fields............................................................................................................. ........18 1.4 ordering information........................................................................................................... .....19 1.4.1 v850es/ sa2 ..................................................................................................................... ..........19 1.4.2 v850es/ sa3 ..................................................................................................................... ..........19 1.5 pin configuration.............................................................................................................. ........20 1.6 function block configuration .......................................... .......................................................24 1.6.1 internal bl ock di agram ......................................................................................................... ........24 1.6.2 internal units................................................................................................................. ...............26 chapter 2 pin functio ns .................................................................................................... ............29 2.1 pin function list.............................................................................................................. .........29 2.2 pin status ..................................................................................................................... .............36 2.3 description of pin functions................................................................................................... 37 2.4 types of pin i/o circuits, i/o buffer power s upplies, and connection of unused pins...49 chapter 3 cpu functio n ..................................................................................................... ............53 3.1 features....................................................................................................................... ..............53 3.2 cpu register set ............................................................................................................... .......54 3.2.1 program regi ster set ........................................................................................................... .........55 3.2.2 system regi ster set............................................................................................................ ..........56 3.3 operation modes ................................................................................................................ ......62 3.4 address space.................................................................................................................. ........63 3.4.1 cpu address space.............................................................................................................. .......63 3.4.2 image .......................................................................................................................... ................64 3.4.3 wrap-around of cpu address s pace...........................................................................................65 3.4.4 memory map ..................................................................................................................... ..........66 3.4.5 areas .......................................................................................................................... .................68 3.4.6 recommended use of address s pace .........................................................................................73 3.4.7 peripheral i/o regist ers....................................................................................................... .........75 3.4.8 special r egister s .............................................................................................................. ............83 3.4.9 notes .......................................................................................................................... .................87 chapter 4 port functio ns ................................................................................................... .........88 4.1 features....................................................................................................................... ..............88 4.1.1 v850es/ sa2 ..................................................................................................................... ..........88 4.1.2 v850es/ sa3 ..................................................................................................................... ..........88 4.2 basic configuration of port.................................................................................................... .89 user?s manual u15905ej2v1ud 9 4.2.1 v850es/ sa2 ..................................................................................................................... .......... 89 4.2.2 v850es/ sa3 ..................................................................................................................... .......... 90 4.3 port configuration......................................................... .................................................... .......91 4.3.1 port 0 ......................................................................................................................... ................. 92 4.3.2 port 2 ......................................................................................................................... ................. 99 4.3.3 port 3 ......................................................................................................................... ............... 106 4.3.4 port 4 ......................................................................................................................... ............... 113 4.3.5 port 7 ......................................................................................................................... ............... 123 4.3.6 port 8 ......................................................................................................................... ............... 125 4.3.7 port 9 ......................................................................................................................... ............... 127 4.3.8 port cd ........................................................................................................................ ............. 143 4.3.9 port cm ........................................................................................................................ ............. 146 4.3.10 port cs ........................................................................................................................ ............. 152 4.3.11 port ct........................................................................................................................ .............. 157 4.3.12 port dh ........................................................................................................................ ............. 162 4.3.13 port dl ........................................................................................................................ .............. 166 4.4 cautions ....................................................................................................................... ...........176 4.4.1 writing data to i/o port ....................................................................................................... ....... 176 4.4.2 reading data fr om i/o port..................................................................................................... ... 176 chapter 5 bus control function.............................. .............................................................1 77 5.1 features....................................................................................................................... ............177 5.2 bus control pins ............................................................................................................... .....177 5.2.1 pin status when internal rom, internal ram, or internal peripher al i/o is a ccessed ................ 178 5.2.2 pin status in eac h operation mode ............................................................................................ 17 8 5.3 memory block function.........................................................................................................1 79 5.3.1 chip select c ontrol f unction ................................................................................................... .... 180 5.4 external bus interface mode control function......... ..........................................................180 5.5 bus access ..................................................................................................................... ........181 5.5.1 number of clo cks for a ccess .................................................................................................... . 181 5.5.2 bus size setti ng func tion...................................................................................................... ...... 181 5.5.3 access by bus si ze............................................................................................................. ....... 182 5.6 wait function.................................................................................................................. ........188 5.6.1 programmable wa it func tion..................................................................................................... . 188 5.6.2 external wait func tion ......................................................................................................... ....... 189 5.6.3 relationship between programmabl e wait and exte rnal wa it..................................................... 190 5.6.4 programmable address wait func tion ........................................................................................ 191 5.7 idle state insertion function ........................................ .........................................................1 92 5.8 bus hold function .............................................................................................................. ...193 5.8.1 functional outlin e ............................................................................................................. ......... 193 5.8.2 bus hold pr ocedur e ............................................................................................................. ...... 194 5.8.3 operation in power save mode ................................................................................................. 19 4 5.9 bus priority ................................................................................................................... ..........195 5.10 boundary operation conditions..................................... ......................................................195 user?s manual u15905ej2v1ud 10 5.10.1 program space .................................................................................................................. ........195 5.10.2 data s pace ..................................................................................................................... ...........195 5.11 bus timing ..................................................................................................................... ........ 196 chapter 6 clock generation function .................... .......................................................... 202 6.1 overview....................................................................................................................... .......... 202 6.2 configuration .................................................................................................................. ....... 203 6.3 control registers.............................................................................................................. ..... 205 6.4 operation...................................................................................................................... .......... 208 6.4.1 operation of each cl ock........................................................................................................ .....208 6.4.2 clock output functi on .......................................................................................................... .......208 6.5 prescaler 3.................................................................................................................... .......... 209 6.5.1 control r egist er ............................................................................................................... ...........210 6.5.2 generation of clock............................................................................................................ ........211 chapter 7 16-bit timer/event counters 0 and 1............................................................. 212 7.1 features....................................................................................................................... ........... 212 7.2 functional overview ............................................................................................................ . 212 7.3 configuration .................................................................................................................. ....... 213 7.4 control registers.............................................................................................................. ..... 217 7.5 operation...................................................................................................................... .......... 222 7.6 application examples ........................................................................................................... 229 7.7 cautions ....................................................................................................................... .......... 238 chapter 8 8-bit timer/event counters 2 to 5 ................................................................. 239 8.1 functional overview ............................................................................................................ . 239 8.2 configuration .................................................................................................................. ....... 240 8.3 control registers.............................................................................................................. ..... 242 8.4 operation...................................................................................................................... .......... 246 8.4.1 operation as interval timer (8 bits)........................................................................................... ..246 8.4.2 operation as external ev ent counter (8 bits )..............................................................................248 8.4.3 square-wave output operati on (8-bit re soluti on)........................................................................ 249 8.4.4 8-bit pwm output operat ion..................................................................................................... ..251 8.4.5 operation as interval timer ( 16 bits ).......................................................................................... .254 8.4.6 operation as external ev ent counter ( 16 bits )............................................................................256 8.4.7 square-wave output operati on (16-bit re soluti on)...................................................................... 257 8.4.8 cauti ons ....................................................................................................................... .............258 chapter 9 real-time counter function.................... .......................................................... 259 9.1 function....................................................................................................................... ........... 259 9.2 control registers.............................................................................................................. ..... 260 9.3 operation...................................................................................................................... .......... 266 9.3.1 initializing count er and c ount-up .............................................................................................. ..266 9.3.2 rewriting count er.............................................................................................................. .........266 user?s manual u15905ej2v1ud 11 9.3.3 controlling interrupt request signal output ................................................................................. 267 9.3.4 notes.......................................................................................................................... ............... 267 chapter 10 watchdog timer func tions...............................................................................269 10.1 functions ...................................................................................................................... ..........269 10.2 configuration .................................................................................................................. ........271 10.3 control registers .............................................................................................................. .....271 10.4 operation...................................................................................................................... ...........274 10.4.1 operation as watchdog ti mer .................................................................................................... 274 10.4.2 operation as in terval timer .................................................................................................... .... 275 10.4.3 oscillation stabilization time selection functi on.......................................................................... 276 chapter 11 a/d converter ................................................................................................... .......277 11.1 function ....................................................................................................................... ...........277 11.2 configuration .................................................................................................................. ........279 11.3 control registers .............................................................................................................. .....281 11.4 operation...................................................................................................................... ...........288 11.4.1 conversion operatio n ........................................................................................................... ..... 288 11.4.2 conversion operation (power fail monitoring functi on) .............................................................. 288 11.5 notes on use ................................................................................................................... .......289 11.6 how to read a/d converter characteristics table.... .........................................................290 chapter 12 d/a converter ................................................................................................... .......294 12.1 functions ...................................................................................................................... ..........294 12.2 configuration .................................................................................................................. ........295 12.3 control registers .............................................................................................................. .....295 12.4 operation...................................................................................................................... ...........297 12.4.1 operation in normal mode....................................................................................................... .. 297 12.4.2 operation in real-t ime output mode ........................................................................................... 29 7 12.4.3 cauti ons ....................................................................................................................... ............. 298 chapter 13 asynchronous serial interface n (uartn)...............................................299 13.1 features....................................................................................................................... ............299 13.1.1 switching modes betw een uart0 and csi1 ............................................................................ 300 13.2 configuration .................................................................................................................. ........301 13.3 control registers .............................................................................................................. .....303 13.4 interrupt requests ............................................................................................................. ....310 13.5 operation...................................................................................................................... ...........311 13.6 dedicated baud rate generator n (brgn) ................ ..........................................................323 13.7 cautions ....................................................................................................................... ...........331 chapter 14 clocked serial interface n (csin) . ...............................................................332 14.1 features....................................................................................................................... ............332 user?s manual u15905ej2v1ud 12 14.1.1 switching modes between csi0 and i 2 c ...................................................................................333 14.1.2 switching modes betw een csi1 and uart0 ............................................................................334 14.2 configuration ............................................................................................................. ............ 334 14.3 control registers.............................................................................................................. ..... 336 14.4 operation...................................................................................................................... .......... 342 14.5 output pins .................................................................................................................... ........ 345 14.6 system configuration example ...................................... ..................................................... 346 chapter 15 i 2 c bus ......................................................................................................................... . 347 15.1 features....................................................................................................................... ........... 347 15.1.1 switching modes between i 2 c and cs i0 ...................................................................................348 15.2 configuration .................................................................................................................. ....... 351 15.3 control registers.............................................................................................................. ..... 353 15.4 i 2 c bus mode functions........................................................................................................ 364 15.5 i 2 c bus definitions and control methods ...................... ..................................................... 365 15.6 i 2 c interrupt request (intiic) ............................................................................................... 372 15.7 interrupt request (intiic) generation timing and wait control...................................... 390 15.8 address match detection method .... ................................................................................... 391 15.9 error detection................................................................................................................ ....... 391 15.10 extension code.......................................................................................................... ........... 391 15.11 arbitration............................................................................................................. ................. 392 15.12 wakeup function ......................................................................................................... ......... 394 15.13 communication reser vation ............................................................................................... 395 15.14 cautions................................................................................................................ ................. 398 15.15 communication operations................................................................................................ . 399 15.16 timing of data communication........................................................................................... 4 01 chapter 16 dma functions (dma controller) ... .............................................................. 408 16.1 features....................................................................................................................... ........... 408 16.2 configuration .................................................................................................................. ....... 409 16.3 control registers.............................................................................................................. ..... 410 16.3.1 dma source address registers 0 to 3 (dsa0 to dsa3 ) .............................................................410 16.3.2 dma destination address register s 0 to 3 (dda 0 to dda 3) ...................................................... 411 16.3.3 dma byte count registers 0 to 3 (dbc0 to dbc3 ) .....................................................................412 16.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3 ) ...................................................413 16.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3 )........................................................414 16.3.6 dma trigger factor registers 0 to 3 (dtfr0 to dtfr 3) ............................................................. 415 16.4 dma bus states ................................................................................................................. .... 417 16.4.1 types of bus states ............................................................................................................ .......417 16.4.2 dmac bus cycle st ate trans ition................................................................................................ 418 16.5 transfer mode .................................................................................................................. ...... 419 16.5.1 single trans fer m ode ........................................................................................................... ......419 16.6 transfer types ................................................................................................................. ...... 419 16.6.1 two-cycle tr ansfer ............................................................................................................. ........419 user?s manual u15905ej2v1ud 13 16.7 transfer object ................................................................................................................ .......420 16.7.1 transfer type and tr ansfer obj ect .............................................................................................. 420 16.7.2 external bus cycles during dma transfer (two-cycl e transfe r) ................................................... 420 16.8 dma channel priorities ......................................................................................................... 421 16.9 dma transfer start factors .............. ....................................................................................421 16.10 dma transfer end ............................................................................................................... ...421 16.10.1 dma transfer end inte rrupt ..................................................................................................... ... 421 16.10.2 terminal count output upon dma trans fer end .......................................................................... 421 16.11 precautions .................................................................................................................... .........422 16.11.1 interrupt factors .............................................................................................................. ........... 424 chapter 17 interrupt/exception processing fu nction ...............................................425 17.1 features....................................................................................................................... ............425 17.2 non-maskable interrupts ........................... ............................................................................4 28 17.2.1 operat ion ...................................................................................................................... ............ 430 17.2.2 restor e........................................................................................................................ .............. 431 17.2.3 np fl ag ........................................................................................................................ .............. 432 17.3 maskable interrupts ............................................................................................................ ...433 17.3.1 operat ion ...................................................................................................................... ............ 433 17.3.2 restor e........................................................................................................................ .............. 435 17.3.3 priorities of ma skable inte rrupts .............................................................................................. .. 436 17.3.4 interrupt control r egister ( xxicn)............................................................................................. ... 440 17.3.5 interrupt mask registers 0 to 2 (imr0 to imr2 ) ......................................................................... 442 17.3.6 in-service priority register (ispr) ............................................................................................ .. 443 17.3.7 id flag........................................................................................................................ ................ 443 17.3.8 watchdog timer mode r egister (w dtm).................................................................................... 444 17.4 noise elimination at external interrupt request input pins ..............................................445 17.4.1 edge detection function of external interrupt reques t input pins ................................................ 445 17.5 software exception ............................................................................................................. ...448 17.5.1 operat ion ...................................................................................................................... ............ 448 17.5.2 restor e........................................................................................................................ .............. 449 17.5.3 ep fl ag ........................................................................................................................ .............. 450 17.6 exception trap ................................................................................................................. ......451 17.6.1 illegal opcode definit ion...................................................................................................... ....... 451 17.6.2 debug tr ap ..................................................................................................................... ........... 453 17.7 interrupt acknowledge time of cpu ....................................................................................455 17.8 periods in which interrupts are not acknowledged by cpu............................................456 chapter 18 standby function...................................... .......................................................... ...457 18.1 overview....................................................................................................................... ...........457 18.2 halt mode...................................................................................................................... ........460 18.2.1 setting and operat ion st atus................................................................................................... ... 460 18.2.2 releasing ha lt m ode ............................................................................................................ .. 460 18.3 idle mode ...................................................................................................................... .........462 user?s manual u15905ej2v1ud 14 18.3.1 setting and operat ion st atus................................................................................................... ...462 18.3.2 releasing id le m ode............................................................................................................ ....462 18.4 software stop mode ............................................................................................................ 4 64 18.4.1 setting and operat ion st atus................................................................................................... ...464 18.4.2 releasing softwar e stop mode ...............................................................................................464 18.5 securing oscillation stabilization time ......................... ..................................................... 466 18.6 subclock operation mode .................................................................................................... 467 18.6.1 setting and operat ion st atus................................................................................................... ...467 18.6.2 releasing subclock operation mode ..........................................................................................467 18.7 sub-idle mode .................................................................................................................. .... 469 18.7.1 setting and operat ion st atus................................................................................................... ...469 18.7.2 releasing sub- idle mode........................................................................................................ .469 18.8 control registers.............................................................................................................. ..... 471 chapter 19 reset function .................................................................................................. ..... 472 19.1 overview....................................................................................................................... .......... 472 19.2 configuration .................................................................................................................. ....... 472 19.3 operation...................................................................................................................... .......... 473 chapter 20 rom correction function....................... .......................................................... 476 20.1 overview....................................................................................................................... .......... 476 20.2 control registers.............................................................................................................. ..... 477 20.2.1 correction address registers 0 to 3 (corad0 to corad3 ) .....................................................477 20.2.2 correction control r egister (c orcn) .........................................................................................478 20.3 rom correction operation and program flow .......... ........................................................ 478 chapter 21 flash memory .................................................................................................... ...... 480 21.1 features....................................................................................................................... ........... 481 21.1.1 erasure unit ................................................................................................................... ............481 21.2 functional overview ............................................................................................................ . 482 21.3 programming environment .................................................................................................. 487 21.4 communication mode ........................................................................................................... 48 8 21.5 pin connection ................................................................................................................. ..... 490 21.5.1 flmd0 pin...................................................................................................................... ...........490 21.5.2 flmd1 pin...................................................................................................................... ...........491 21.5.3 serial inte rface pin........................................................................................................... ..........491 21.5.4 reset pin...................................................................................................................... ...........494 21.5.5 port pins (i ncluding nmi) ...................................................................................................... .....494 21.5.6 other signal pins.............................................................................................................. ..........494 21.5.7 power s upply ................................................................................................................... ..........494 21.6 programming method............................................................................................................ 4 95 21.6.1 flash memory cont rol ........................................................................................................... .....495 21.6.2 flash memory pr ogramming mode ............................................................................................496 21.6.3 selection of comm unication mode .............................................................................................497 user?s manual u15905ej2v1ud 15 21.6.4 communication command ......................................................................................................... 4 97 21.7 rewriting by self programming........ ....................................................................................499 21.7.1 overvi ew ....................................................................................................................... ............ 499 21.7.2 featur es ....................................................................................................................... ............. 500 chapter 22 electrical specifications..................... .............................................................503 chapter 23 package drawings....................................... ......................................................... .532 chapter 24 recommended soldering conditions .. .........................................................534 appendix a register index .................................................................................................. ........536 appendix b instruction set list........................................................................................... ...543 b.1 conventions.................................................................................................................... ........543 b.2 instruction set (in alphabetical order) ................... .............................................................546 appendix c revision history ................................................................................................ ......553 c.1 major revisions in this edition ............................................................................................553 user?s manual u15905ej2v1ud 16 chapter 1 introduction the v850es/sa2 and v850es/sa3 are low-power models of the nec electronics v850 series of single-chip microcontrollers for real-time control. 1.1 overview the v850es/sa2 and v850es/sa3 are 32-bit single-chip mi crocontrollers that employ the v850es cpu core and integrate peripheral functions such as rom/ram, timers /counters, serial interfaces, an a/d converter, a d/a converter, and a dma controller. these products are part of the v850/ sa1 line of low-power microcontrollers, but employ the v850es as the cpu and have additional peripheral functions such as a d/a converter and rom correction. they also realized lower voltage and power consumption. the v850es/sa2 and v850es/sa3 feature instructions idea l for digital servo control applications, such as multiplication instructions using a hardware multiplier , saturated operation instructions, and bit manipulation instructions, as well as basic instructions with a shor t real-time response speed and a 1-clock pitch. these microcontrollers can be used in real -time control systems requiring low powe r consumption, such as dvc and portable audio systems, with a high cost effectiveness. table 1-1 shows the products in the v850es/sa2 and v850es/sa3 lineup. table 1-1. v850es/sa2 and v850es/sa3 product lineup product name rom commercial name part number i 2 c type size ram size package pd703200 none pd703200y provided 128 kb 8 kb pd703201 none pd703201y provided mask rom pd70f3201 none v850es/sa2 pd70f3201y provided flash memory 256 kb 16 kb 100-pin tqfp (14 14) pd703204 none pd703204y provided mask rom pd70f3204 none v850es/sa3 pd70f3204y provided flash memory 256 kb 16 kb 121-pin fbga (12 12) chapter 1 introduction user?s manual u15905ej2v1ud 17 1.2 features number of instructions 83 minimum instruction execution time 50 ns: main clock = 20 mhz ( pd703200, 703201, 703204, 70f3201, 70f3204) 59 ns: main clock = 17 mhz ( pd703200y, 703201y, 703204y, 70f3201y, 70f3204y) 30.5 s: subclock = 32.768 khz general-purpose registers 32 bits 32 registers instruction set signed multiplication (16 16 32): 1 to 2 clocks signed multiplication (32 32 64): 1 to 5 clocks saturated operation (with overflow/underflow detection function) 32-bit shift instruction: 1 clock bit manipulation instruction load/store instruction with long/short format memory space 64 mb linear address space (for program/data) external expansion: up to 4 mb for v850es/sa2 and 16 mb for v850es/sa3 (of which 1 mb is used as internal rom/ram space) memory block division function: 2, 2, 4, 8 mb (total: 4 blocks) programmable wait function idle state insertion function external bus interface multiplex ed bus/separate bus output selectable 8/16-bit data bus sizing function 4-space chip select function wait functions ? programmable wait function ? external wait function idle state function bus hold function internal memory ram: 16 kb ( pd703201, 703201y, 70f3201, 70f3201y, 703204, 703204y, 70f3204, 70f3204y) 8 kb ( pd703200, 703200y) mask rom: 256 kb ( pd703201, 703201y, 703204, 703204y) 128 kb ( pd703200, 703200y) flash memory: 256 kb ( pd70f3201, 70f3201y , 70f3204, 70f3204y) chapter 1 introduction user?s manual u15905ej2v1ud 18 interrupts/exceptions external interrupts: 8 sources internal interrupts: 30 sources ( pd703200, 703201, 70f3201) 31 sources ( pd703200y, 703201y, 70f3201y) 31 sources ( pd703204, 70f3204) 32 sources ( pd703204y, 70f3204y) software exception: 32 sources exception trap: 1 source i/o lines total: 82 (input ports: 14, i/o ports: 68) (v850es/sa2) 102 (input ports: 18, i/o ports: 84) (v850es/sa3) timer/counter 16-bit timer/event counter: 2 ch (pwm output) 8-bit timer/event counter: 4 ch (connectable in cascade) real-time counter (for watch) subclock/main clock operation: 1 ch dedicated on-chip hardware counter for weeks, days, hours, minutes, and seconds up to 4,095 weeks can be counted watchdog timer: 1 ch serial interface asynchronous serial interface (uart) clocked serial interface (csi) i 2 c bus interface (i 2 c) ( pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only) csi/uart: 1 ch uart: 1 ch csi/i 2 c: 1 ch csi: 2 ch (v850es/sa2), 3 ch (v850es/sa3) a/d converter 10-bit resolution: 12 ch (v850es/sa2) 16 ch (v850es/sa3) d/a converter 8-bit resolution: 2 ch dma controller: 4 ch (transfer object: internal memory, on-chip peripheral i/o, and external memory) rom correction: 4 places specifiable clock generator main clock/subclock operation cpu clock: 7 steps (f x , f x /2, f x /4, f x /8, f x /16, f x /32, f xt ) power save function halt/idle/stop mode package 100-pin plastic tqfp (fine pitch) (14 14) (v850es/sa2) 121-pin plastic fbga (12 12) (v850es/sa3) 1.3 application fields mobile devices requiring low power consumption example dvc and portable audio systems chapter 1 introduction user?s manual u15905ej2v1ud 19 1.4 ordering information 1.4.1 v850es/sa2 part number package internal rom pd703200gc- -yeu-a 100-pin plastic tqfp (fine pitch) (14 14) mask rom (128 kb) pd703200ygc- -yeu-a 100-pin plastic tqfp (fine pitch) (14 14) mask rom (128 kb) pd703201gc- -yeu-a 100-pin plastic tqfp (fine pitch) (14 14) mask rom (256 kb) pd703201ygc- -yeu-a 100-pin plastic tqfp (fine pitch) (14 14) mask rom (256 kb) pd70f3201gc-yeu-a 100-pin plastic tqfp (fine pitch) (14 14) flash memory (256 kb) pd70f3201ygc-yeu-a 100-pin plastic tqfp (fine pitch) (14 14) flash memory (256 kb) remarks 1. indicates rom code suffix. 2. no romless model is available. 3. products with -a at the end of the part number are lead-free products. 1.4.2 v850es/sa3 part number package internal rom pd703204f1- -ea6-a 121-pin plastic fbga (12 12) mask rom (256 kb) pd703204yf1- -ea6-a 121-pin plastic fbga (12 12) mask rom (256 kb) pd70f3204f1-ea6-a 121-pin plastic fbga (12 12) flash memory (256 kb) pd70f3204yf1-ea6-a 121-pin plastic fbga (12 12) flash memory (256 kb) remarks 1. indicates rom code suffix. 2. no romless model is available. 3. products with -a at the end of the part number are lead-free products. chapter 1 introduction user?s manual u15905ej2v1ud 20 1.5 pin configuration v850es/sa2 100-pin plastic tqfp (fine pitch) (14 14) ? pd703200gc- -yeu-a ? pd703201gc- -yeu-a ? pd70f3201gc-yeu-a ? pd703200ygc- -yeu-a ? pd703201ygc- -yeu-a ? pd70f3201ygc-yeu-a top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 p05/intp4 p04/intp3/ti5 p03/intp2/ti4 p02/intp1/ti3 p01/intp0/ti2 p46/intp11/to1 p45/intp10/ti1/tclr1 p44/intp01/to0 p43/intp00/ti0/tclr0 p42/sck0/scl note 1 p41/so0/sda note 1 p40/si0 pdh5/a21 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p96/a6/to4 p97/a7/to5 p98/a8/rxd1 p99/a9/txd1 p910/a10/si2 p911/a11/so2 p912/a12/sck2 p913/a13/si3 p914/a14/so3 p915/a15/sck3 ev ss ev dd pcs0/cs0 pcs1/cs1 pcs2/cs2 pcs3/cs3 pcm0/wait pcm1/clkout pcm2/hldak pcm3/hldrq pct0/wr0 pct1/wr1 pct4/rd pct5 pct6/astb 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 av ref0 av dd av ss p80/ano0 p81/ano1 av ref1 p00/nmi p30/si1/rxd0 p31/so1/txd0 p32/sck1 v dd v ss x1 x2 reset xt1 xt2 v ss v dd p90/a0 p91/a1 p92/a2/intp5 p93/a3/intp6 p94/a4/to2 p95/a5/to3 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 ev dd ev ss ic/flmd0 notes 2, 3 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 note 2 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 pct7 notes 1. scl and sda are valid only in the pd703200y, 703201y, and 70f3201y. 2. flmd0 and flmd1 are valid only in the pd70f3201 and 70f3201y. 3. ic: directly connect this pin to v ss ( pd703200, 703200y, 703201 and 703201y). flmd0: connect this pin to v ss in the normal operation mode ( pd70f3201 and 70f3201y). chapter 1 introduction user?s manual u15905ej2v1ud 21 v850es/sa3 121-pin plastic fgba (12 12) pd703204f1- -ea6-a pd70f3204f1-ea6-a pd703204yf1- -ea6-a pd70f3204yf1-ea6-a top view bottom view nmlkjhgfedcba abcdefghjklmn 13 12 11 10 9 8 7 6 5 4 3 2 1 pin no. name pin no. name pin no. name a1 p70/ani0 b8 pcd3 d2 av ref1 a2 p71/ani1 b9 p02/intp1/ti3 d3 p00/nmi a3 p73/ani3 b10 p46/intp11/to1 d11 pdh0/a16 a4 p713/ani13 b11 p42/sck0/scl note d12 pdh2/a18 a5 p76/ani6 b12 p40/si0 d13 pdh1/a17 a6 p78/ani8 b13 pdh4/a20 e1 p30/si1/rxd0 a7 p711/ani11 c1 p80/ano0 e2 p31/so1/txd0 a8 p04/intp3/ti5 c2 av ss e3 p32/sck1 a9 pcd2 c3 p74/ani4 e11 pdl14/ad14 a10 p45/intp10/ti1/tclr1 c4 p714/ani14 e12 pdh6/a22 a11 p43/intp00/ti0/tclr0 c5 p715/ani15 e13 pdl15/ad15 a12 p41/so0/sda note c6 p79/ani9 f1 v ss a13 pdh5/a21 c7 p05/intp4 f2 x1 b1 av dd c8 p03/intp2/ti4 f3 v dd b2 av ref0 c9 pcd1 f11 pdl11/ad11 b3 p72/ani2 c10 p01/intp0/ti2 f12 pdl13/ad13 b4 p712/ani12 c11 p44/intp01/to0 f13 pdl12/ad12 b5 p75/ani5 c12 pdh3/a19 g1 reset b6 p77/ani7 c13 pdh7/a23 g2 xt1 b7 p710/ani10 d1 p81/ano1 g3 x2 note scl and sda are valid only in the pd703204y and 70f3204y. remark leave the d4 pin open. chapter 1 introduction user?s manual u15905ej2v1ud 22 (2/2) pin no. name pin no. name pin no. name g11 ev ss k13 pdl3/ad3 m7 pcs4 g12 pdl10/ad10 l1 p93/a3/intp6 m8 pcm0/wait g13 ev dd l2 p94/a4/to2 m9 pcm2/hldak h1 v ss l3 p911/a11/so2 m10 pct3 h2 v dd l4 p914/a14/so3 m11 pct4/rd h3 xt2 l5 p915/a15/sck3 m12 pct7 h11 pdl8/ad8 l6 ev dd m13 pdl0/ad0 h12 ic/flmd0 notes 1, 2 l7 pcs0/cs0 n1 p96/a6/to4 h13 pdl9/ad9 l8 pcs2/cs2 n2 p98/a8/rxd1 j1 p20/si4 l9 pcm4 n3 p910/a10/si2 j2 p91/a1 l10 pct2 n4 p912/a12/sck2 j3 p90/a0 l11 pct0/wr0 n5 pcs7 j11 pdl5/ad5/flmd1 note 1 l12 pdl1/ad1 n6 pcs6 j12 pdl7/ad7 l13 pdl2/ad2 n7 pcs1/cs1 j13 pdl6/ad6 m1 p95/a5/to3 n8 pcs3/cs3 k1 p22/sck4 m2 p97/a7/to5 n9 pcm5 k2 p92/a2/intp5 m3 p99/a9/txd1 n10 pcm3/hldrq k3 p21/so4 m4 p913/a13/si3 n11 pct1/wr1 k11 pcm1/clkout m5 ev ss n12 pct5 k12 pdl4/ad4 m6 pcs5 n13 pct6/astb notes 1. flmd0 and flmd1 are valid only in the pd70f3204 and 70f3204y. 2. ic: directly connect this pin to v ss ( pd703204 and 703204y). flmd0: connect this pin to v ss in the normal operation mode ( pd70f3204 and 70f3204y). chapter 1 introduction user?s manual u15905ej2v1ud 23 pin identification a0 to a23: ad0 to ad15: ani0 to ani15: ano0, ano1: astb: av dd : av ref0 , av ref1 : av ss : clkout: cs0 to cs3: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: ic: intp0 to intp6: intp00, intp01: intp10, intp11 nmi: p00 to p05: p20 to p22: p30 to p32: p40 to p46: p70 to p715: p80, p81: address bus address/data bus analog input analog output address strobe analog v dd analog reference voltage analog v ss clock output chip select power supply for port ground for port flash programming mode hold acknowledge hold request internally connected external interrupt input interrupt request to timer non-maskable interrupt request port 0 port 2 port 3 port 4 port 7 port 8 p90 to p915: pcd1 to pcd3: pcm0 to pcm5: pcs0 to pcs7: pct0 to pct7: pdh0 to pdh7: pdl0 to pdl15: rd: reset: rxd0, rxd1: sck0 to sck4: scl: sda: si0 to si4: so0 to so4: tclr0, tclr1: ti0 to ti5: to0 to to5: txd0, txd1: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port 9 port cd port cm port cs port ct port dh port dl read strobe reset receive data serial clock serial clock serial data serial input serial output timer clear input timer input timer output transmit data power supply ground wait lower byte write strobe higher byte write strobe crystal for main clock crystal for subclock chapter 1 introduction user?s manual u15905ej2v1ud 24 1.6 function block configuration 1.6.1 internal block diagram ? v850es/sa2 nmi intp00, intp01, intp10, intp11 to0, to1 ti0, ti1 tclr0, tclr1 so0 to so3 si0 to si3 sck0 to sck3 intp0 to intp6 intc timer/counter 16-bit timer: 2 ch to2 to to5 ti2 to ti5 txd0, txd1 rxd0, rxd1 uart: 2 ch sda note 3 scl note 3 i 2 c note 3 : 1 ch dmac note 1 note 2 ram rom pc alu cpu hldrq hldak astb rd wait wr0, wr1 cs0 to cs3 a0 to a21 ad0 to ad15 ic note 4 flmd0 note 4 , flmd1 note 5 cg rg a/d converter d/a converter pcs0 to pcs3 pcm0 to pcm3 pct0, pct1, pct4 to pct7 pdh0 to pdh5 pdl0 to pdl15 p90 to p915 p80, p81 p70 to p711 p40 to p46 p30 to p32 p00 to p05 ano0, ano1 av ref1 av dd av ref0 av ss ani0-ani11 clkout x1 x2 xt1 xt2 reset v dd v ss ev dd ev ss bcu csi: 4 ch port rom correction timer/counter 8-bit timer: 4 ch real-time counter watchdog timer instruction queue 32-bit barrel shifter multiplier 16 16 32 system registers general-purpose registers 32 bits 32 notes 1. pd703200, 703200y: 128 kb (mask rom) pd703201, 703201y: 256 kb (mask rom) pd70f3201, 70f3201y: 256 kb (flash memory) 2. pd703200, 703200y: 8 kb pd703201, 703201y, 70f3201, 70f3201y: 16 kb 3. pd703200y, 703201y, and 70f3201y only 4. pd703200, 703200y, 703201, and 703201y only 5. pd70f3201 and 70f3201y only chapter 1 introduction user?s manual u15905ej2v1ud 25 ? v850es/sa3 nmi intp00, intp01, intp10, intp11 to0, to1 ti0, ti1 tclr0, tclr1 so0 to so4 si0 to si4 sck0 to sck4 intp0 to intp6 intc to2 to to5 ti2 to ti5 txd0, txd1 rxd0, rxd1 uart: 2 ch sda note 2 scl note 2 i 2 c note 2 : 1 ch dmac note 1 ram rom 16 kb pc alu cpu hldrq hldak astb rd wait wr0, wr1 cs0 to cs3 a0 to a23 ad0 to ad15 ic note 3 flmd0 note 4 , flmd1 note 4 cg rg pcs to pcs7 pcm0 to pcm5 pct0 to pct7 pdh0 to pdh7 pdl0 to pdl15 pcd1 to pcd3 p90 to p915 p80, p81 p70 to p715 p40 to p46 p30 to p32 p20 to p22 p00 to p05 ano0, ano1 av ref1 av dd av ref0 av ss ani0 to ani15 clkout x1 x2 xt1 xt2 reset v dd v ss ev dd ev ss bcu csi: 5 ch rom correction timer/counter 16-bit timer: 2 ch timer/counter 8-bit timer: 4 ch instruction queue 32-bit barrel shifter multiplier 16 16 32 system registers general-purpose registers 32 bits 32 a/d converter d/a converter port real-time counter watchdog timer notes 1. pd703204, 703204y: 256 kb (mask rom) pd70f3204, 70f3204y: 256 kb (flash memory) 2. pd703204y and 70f3204y only 3. pd703204 and 703204y only 4. pd70f3204 and 70f3204y only chapter 1 introduction user?s manual u15905ej2v1ud 26 1.6.2 internal units (1) cpu the cpu can execute almost all instruction processing , such as address calculation, arithmetic logic operations, and data transfer, with 1 clock, using a 5-stage pipeline. the cpu has dedicated hardware units such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) to speed up complicated instruction processing. (2) bus control unit (bcu) the bcu starts the required external bus cycles in a ccordance with the physical address obtained by the cpu. if the cpu does not request the start of a bus cycle when an instruction is fetched from the external memory area, the bcu generates a prefetch address and prefetch es an instruction code. the prefetched instruction code is loaded to the internal instruction queue. (3) rom this is a 256 kb or 128 kb mask rom or flash memory mapped to addresses 0000000h to 003ffffh or 0000000h to 001ffffh. the cpu c an access the rom with 1 clock wh en an instruction is fetched. (4) ram this is a 16 kb or 8 kb ram mapped to addresse s 3ffb000h to 3ffefffh or 3ffd000h to 3ffefffh. it can be accessed by the cpu with 1 clock when data is accessed. (5) interrupt controller (intc) the intc processes hardware interrupt requests (nmi, in tp0 to intp6) from the internal peripheral hardware and external sources. eight levels of priority can be sp ecified for these interrupt requests. multiple interrupts can also be processed. (6) clock generator (cg) two oscillators, one for the main clock (f x ) and the other for the subclock (f xt ), are provided. seven types of clocks (f x , f x /2, f x /4, f x /8, f x /16, f x /32, and f xt ) can be generated, of which one is supplied to the cpu as the operation clock (f cpu ). the subclock can be selected only as the operation clock for the real-time counter. (7) timer/counter a two-channel 16-bit timer/event counter and four-channel 8-bit timer/event counter are available, enabling pulse interval and frequency measurement and programmable pulse output. two 8-bit timer/event counter channels can be connected in cascade and used as a 16-bit timer. (8) real-time counter (for watch) this counter counts the reference time (1 second) for t he watch count from the subclock (32.768 khz) or main clock. it can also be used as an interval timer that operates with the main clock. dedicated hardware counters for counting weeks, days, hours, minutes, and seconds, are provided, and up to 4095 weeks can be counted. (9) watchdog timer a watchdog timer that detects program han g-up and system errors is provided. this watchdog timer can also be used as an interval timer. when used as a watchdog timer, a non-maskable inte rrupt request (intwdt) is generated if the watchdog timer overflows. when used as an interval timer, a maskable interrupt request is generated when the timer overflows. chapter 1 introduction user?s manual u15905ej2v1ud 27 (10) serial interface (sio) the v850es/sa2 and v850es/sa3 have asynchronous serial interfaces (uart0 and uart1), clocked serial interfaces (v850es/sa2: csi0 to csi3 , v850es/sa3: csi0 to csi4), and an i 2 c bus interface (i 2 c) as the serial interfaces. the v850es/sa2 can use up to four channels, and the v850es/sa3 can use up to five channels at the same time. of these channels, one can be switched between uart and csi, and another can be switched between csi and i 2 c. uart0 and uart1 transfer data using the txd0, txd1, rxd0, and rxd1 pins. csi0 to csi3 transfer data using the so0 to so3, si0 to si3, and sck0 to sck3 pins. csi4 transfers data using the so4, si 4, and sck4 pins (v850es/sa3 only). i 2 c transfers data using the sda and scl pins. i 2 c is provided only in the pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y. uart includes a dedicated baud rate generator. (11) a/d converter the v850es/sa2 and v850es/sa3 have a high-speed high-resolution, 10-bit a/d converter with 12 and 16 analog input pins, respectively. the a/d converter in both products is a successive approximation type. (12) d/a converter a two-channel 8-bit resolution r-string d/a converter is provided. (13) dma controller a dma controller with four channels is provided. this dma controller transfers data between the internal ram, on-chip peripheral i/o, and external memory, in response to interrupt requests from the on-chip peripheral i/o. (14) rom correction this is a function to replace part of the program in the mask rom with program in the internal ram for execution. the program can be corrected at up to four places. chapter 1 introduction user?s manual u15905ej2v1ud 28 (15) ports some port pins have a control function as well as a general-purpose port function, as shown below. port i/o port function control function p0 6-bit i/o nmi, external interrupt, timer input p2 note 3-bit i/o serial interface p3 3-bit i/o serial interface p4 7-bit i/o serial interface, timer i/o, timer trigger p7 12-bit input (v850es/sa2) 16-bit input (v850es/sa3) a/d converter analog input p8 2-bit input d/a converter analog output p9 16-bit i/o external address bus, serial interface, timer output, external interrupt pcd note 3-bit i/o ? pcm 4-bit i/o (v850es/sa2) 6-bit i/o (v850es/sa3) external bus interface pcs 4-bit i/o (v850es/sa2) 8-bit i/o (v850es/sa3) chip select output pct 6-bit i/o (v850es/sa2) 8-bit i/o (v850es/sa3) external bus interface pdh 6-bit i/o (v850es/sa2) 8-bit i/o (v850es/sa3) external address bus pdl 16-bit i/o general-purpose port external address/data bus note v850es/sa3 only user?s manual u15905ej2v1ud 29 chapter 2 pin functions 2.1 pin function list this chapter explains the names and functions of the pins in the v850es/sa2 and v850es/sa3, classified into port pins and non-port pins. two power supplies are available for the pin i/o buffers: av dd and ev dd . the relationship between the power supplies and pins is shown below. table 2-1. i/o buffer power supply for each pin power supply corresponding pin av dd port 7, port 8 ev dd port 0, port 2, port 3, port 4, port 9, port cd, port cm, port cs, port ct, port dh, port dl, reset the differences in the pins of the v8 50es/sa2 and v850es/sa3 are shown below. table 2-2. differences in pi ns of v850es/sa2 and v850es/sa3 v850es/sa2 v850es/sa3 pin pd703201, pd703200 pd70f3201 pd703201y, pd703200y pd70f3201y pd703204 pd70f3204 pd703204y pd70f3204y p20/si4, p21/so4, p22/sck4 none provided p712/ani12 to p715/ani15 none provided pcd1 to pcd3 none provided pcm4, pcm5 none provided pcs4 to pcs7 none provided pct2, pct3 none provided pdh6/a22, pdh7/a23 none provided sda, sda none provided none provided flmd0, flmd1 none provided none provided none provided none provided ic provided none provided none provided none provided none chapter 2 pin functions user?s manual u15905ej2v1ud 30 (1) port pins (1/3) pin name i/o on-chip pull-up resistor function alternate-function pin p00 nmi p01 intp0/ti2 p02 intp1/ti3 p03 intp2/ti4 p04 intp3/ti5 p05 i/o provided port 0. 6-bit i/o port. can be set to input or output in 1-bit units. intp4 [p20] [si4] [p21] [so4] [p22] i/o provided port 2. 3-bit i/o port. can be set to input or output in 1-bit units. can be specified as an n-ch open drain port in 1-bit units (p21 and p22 only). [sck4] p30 si1/rxd0 p31 so1/txd0 p32 i/o provided port 3. 3-bit i/o port. can be set to input or output in 1-bit units. can be specified as an n-ch open drain port in 1-bit units (p31 and p32 only). sck1 p40 si0 p41 so0/sda note p42 sck0/scl note p43 intp00/ti0/tclr0 p44 intp01/to0 p45 intp10/ti1/tclr1 p46 i/o provided port 4. 7-bit i/o port. can be set to input or output in 1-bit units. can be specified as an n-ch open drain port in 1-bit units (p41 and p42 only). intp11/to1 p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 ani7 p78 ani8 p79 ani9 p710 ani10 p711 ani11 [p712] [ani12] [p713] [ani13] [p714] [ani14] [p715] input none port 7. 12-bit input port (v850es/sa2). 16-bit input port (v850es/sa3). [ani15] note pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only remark [ ]: pins provided only in the v850es/sa3 chapter 2 pin functions user?s manual u15905ej2v1ud 31 (2/3) pin name i/o on-chip pull-up resistor function alternate-function pin p80 ano0 p81 input none port 8. 2-bit input port ano1 p90 a0 p91 a1 p92 a2/intp5 p93 a3/intp6 p94 a4/to2 p95 a5/to3 p96 a6/to4 p97 a7/to5 p98 a8/rxd1 p99 a9/txd1 p910 a10/si2 p911 a11/so2 p912 a12/sck2 p913 a13/si3 p914 a14/so3 p915 i/o provided port 9. 16-bit i/o port. can be set to input or output in 1-bit units. can be specified as an n-ch open drain port in 1-bit units (p911, p912, p914, and p915 only). a15/sck3 [pcd1] ? [pcd2] ? [pcd3] i/o none port cd. 3-bit i/o port. can be set to input or output in 1-bit units. ? pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq [pcm4] ? [pcm5] i/o none port cm. 4-bit i/o port (v850es/sa2). 6-bit i/o port (v850es/sa3). can be set to input or output in 1-bit units. ? pcs0 cs0 pcs1 cs1 pcs2 cs2 pcs3 cs3 [pcs4] ? [pcs5] ? [pcs6] ? [pcs7] i/o none port 10. 4-bit i/o port (v850es/sa2). 8-bit i/o port (v850es/sa3). can be set to input or output in 1-bit units. ? pct0 wr0 pct1 wr1 [pct2] ? [pct3] ? pct4 rd pct5 ? pct6 astb pct7 i/o none port ct. 6-bit i/o port (v850es/sa2). 8-bit i/o port (v850es/sa3). can be set to input or output in 1-bit units. ? remark [ ]: pins provided only in the v850es/sa3 chapter 2 pin functions user?s manual u15905ej2v1ud 32 (3/3) pin name i/o on-chip pull-up resistor function alternate-function pin pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 pdh5 a21 [pdh6] [a22] [pdh7] i/o none port dh. 6-bit i/o port (v850es/sa2). 8-bit i/o port (v850es/sa3). can be set to input or output in 1-bit units. [a23] pdl0 ad0 pdl1 ad1 pdl2 ad2 pdl3 ad3 pdl4 ad4 pdl5 ad5/flmd1 note pdl6 ad6 pdl7 ad7 pdl8 ad8 pdl9 ad9 pdl10 ad10 pdl11 ad11 pdl12 ad12 pdl13 ad13 pdl14 ad14 pdl15 i/o none port dl. 16-bit i/o port. can be set to input or output in 1-bit units. ad15 note pd70f3201, 70f3201y, 70f3204, and 70f3204y only remark [ ]: pins provided only in the v850es/sa3 chapter 2 pin functions user?s manual u15905ej2v1ud 33 (2) non-port pins (1/3) pin name i/o on-chip pull-up resistor function alternate- function pin a0 p90 a1 p91 a2 p92/intp5 a3 p93/intp6 a4 p94/to2 a5 p95/to3 a6 p96/to4 a7 p97/to5 a8 p98/rxd1 a9 p99/txd1 a10 p910/si2 a11 p911/so2 a12 p912/sck2 a13 p913/si3 a14 p914/so3 a15 output provided address bus for external memory (when separate bus is used) p915/sck3 a16 to a21, [a22, a23] output none address bus for external memory pdh0 to pdh5, [pdh6, pdh7] ad0 to ad4 pdl0 to pdl4 ad5 pdl5/flmd1 note ad6 to ad15 i/o none address/data bus for external memory pdl6 to pdl15 ani0 p70 ani1 p71 ani2 p72 ani3 p73 ani4 p74 ani5 p75 ani6 p76 ani7 p77 ani8 p78 ani9 p79 ani10 p710 ani11 p711 [ani12] [p712] [ani13] [p713] [ani14] [p714] [ani15] input none analog voltage input for a/d converter [p715] ano0 p80 ano1 output none analog voltage output for d/a converter p81 astb output none address strobe signal output for external memory pct6 note pd70f3201, 70f3201y, 70f3204, and 70f3204y only remark [ ]: pins provided only in the v850es/sa3 chapter 2 pin functions user?s manual u15905ej2v1ud 34 (2/3) pin name i/o on-chip pull-up resistor function alternate- function pin av dd ? ? positive power supply for a/d converter (same potential as v dd ) ? av ref0 reference voltage input for a/d converter ? av ref1 input ? reference voltage input for d/a converter ? av ss ? ? ground potential for a/d and d/a converters (same potential as v ss ) ? clkout output none internal system clock output pcm1 cs0 to cs3 output none chip select output pcs0 to pcs3 ev dd ? ? positive power supply for external device (same potential as v dd ) ? ev ss ? ? ground potential for external device (same potential as v ss ) ? flmd0 note 1 ? flmd1 note 1 input none flash programming mode setting pin pdl5/ad5 hldak output none bus hold acknowledge output pcm2 hldrq input none bus hold request input pcm3 ic ? ? internally connected (connect this pin directly to v ss ) ( pd703200, 703200y, 703201, 703201y, 703204, and 703204y only) ? intp0 to intp3 p01/ti2 to p04/ti5 intp4 p05 intp5 p92/a2 intp6 input provided external interrupt request input (maskable, analog noise elimination) p93/a3 intp00 p43/ti0/tclr0 intp01 capture trigger input (tm0) p44/to0 intp10 p45/ti1/tclr1 intp11 input provided capture trigger input (tm1) p46/to1 nmi input provided external interrupt input (non-maskable, analog noise elimination) p00 rd output none read strobe signal output for external memory pct4 reset input ? system reset input ? rxd0 serial receive data input (uart0) p30/si1 rxd1 input provided serial receive data input (uart1) p98/a8 sck0 serial clock i/o (csi0) p42/scl note 2 sck1 serial clock i/o (csi1) p32 sck2 serial clock i/o (csi2) p912/a12 sck3 serial clock i/o (csi3) p915/a15 [sck4] i/o provided serial clock i/o (csi4) [p22] scl note 2 i/o provided serial clock i/o (i 2 c) p42/sck0 sda note 2 i/o provided serial transmit/receive data i/o (i 2 c) p41/so0 si0 serial receive data input (csi0) p40 si1 serial receive data input (csi1) p30/rxd0 si2 serial receive data input (csi2) p910/a10 si3 serial receive data input (csi3) p913/a13 [si4] input provided serial receive data input (csi4) [p20] notes 1. pd70f3201, 70f3201y, 70f3204, and 70f3204y only 2. pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only remark [ ]: pins provided only in the v850es/sa3 chapter 2 pin functions user?s manual u15905ej2v1ud 35 (3/3) pin name i/o on-chip pull-up resistor function alternate-function pin so0 serial transmit data output (csi0) p41/sda note so1 serial transmit data output (csi1) p31/txd0 so2 serial transmit data output (csi2) p911/a11 so3 serial transmit data output (csi3) p914/a14 [so4] output provided serial transmit data output (csi4) [p21] tclr0 timer clear input (tm0) p43/intp00/ti0 tclr1 input provided timer clear input (tm1) p45/intp10/ti1 ti0 external event/clock input (tm0) p43/intp00/tclr0 ti1 external event/clock input (tm1) p45/intp10/tclr1 ti2 external event/clock input (tm2) p01/intp0 ti3 external event/clock input (tm3) p02/intp1 ti4 external event/clock input (tm4) p03/intp2 ti5 input provided external event/clock input (tm5) p04/intp3 to0 timer output (tm0) p44/intp01 to1 timer output (tm1) p46/intp11 to2 timer output (tm2) p94/a4 to3 timer output (tm3) p95/a5 to4 timer output (tm4) p96/a6 to5 output provided timer output (tm5) p97/a7 txd0 serial transmit data output (uart0) p31/so1 txd1 output provided serial transmit data output (uart1) p99/a9 v dd ? ? positive power supply pin for internal circuits ? v ss ? ? ground potential for internal circuits ? wait input none external wait input pcm0 wr0 write strobe for external memory (lower 8 bits) pct0 wr1 output none write strobe for external memory (higher 8 bits) pct1 x1 input ? x2 ? none oscillator connection for main clock ? xt1 input ? xt2 ? none oscillator connection for subclock ? note pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only remark [ ]: pins provided only in the v850es/sa3 chapter 2 pin functions user?s manual u15905ej2v1ud 36 2.2 pin status the operating status of each pin in each operation mode is shown below. table 2-3. operating status of each pin in each operation mode bus control pins reset halt mode or dma transfer idle and stop modes idle state note 2 bus hold ad0 to ad15 note 3 a16 to a23 undefined note 4 a0 to a15 undefined hi-z retained hi-z wait ? ? ? ? clkout operates l operates operates cs0 to cs3 retained wr0, wr1 rd astb h hi-z hldak h h l hldrq hi-z note 1 operates ? ? operates notes 1. because the bus control pins function alternately as port pins, they are initialized to the input mode (port mode). 2. indicates the pin status in the idle st ate that is inserted after the t3 state. 3. in separate mode: hi-z in multiplexed mode: undefined 4. in separate mode only remark hi-z: high impedance retained: status in external bus cycle immediately before is retained. l: low-level output h: high-level output ? : input not sampled (not acknowledged) chapter 2 pin functions user?s manual u15905ej2v1ud 37 2.3 description of pin functions (1) p00 to p05 (port 0) ? 3-state i/o port 0 is a 6-bit i/o port that can be set to the input or output in 1-bit units. besides functioning as i/o port pins, p00 to p05 also operate as nmi input, external interrupt request, and timer/counter input pins. port or control mode can be selected as the operation mode for each bit, with the valid edge of each pin specified by using the intr0 and intf0 registers. (a) port mode p00 to p05 can be set to the input or output mode in 1-bit units by using port mode register 0 (pm0). (b) control mode (i) nmi (non-maskable interrupt request) ? input this pin inputs a non-maskable interrupt request. (ii) intp0 to intp4 (interrupt request from peripherals) ? input these pins input an external interrupt request. (iii) ti2 to ti5 (timer input 2 to 5) ? input these pins input an external count clock to timers 2 to 5. (2) p20 to p22 (port 2) (v850es/sa3 only) ? 3-state i/o port 2 is a 3-bit i/o port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, p20 to p22 also operate as the i/o pins of the serial interface. these pins can be set to the port or control mode in 1-bit units. the output mode of p21 and p22 can also be se t to normal output or n-ch open-drain output. (a) port mode p20 to p22 can be set to the input or output mode in 1-bit units by using port mode register 2 (pm2). (b) control mode (i) si4 (serial input 4) ? input this pin inputs the serial receive data of csi4. (ii) so4 (serial output 4) ? output this pin outputs the serial transmit data of csi4. (iii) sck4 (serial clock 4) ? 3-state i/o this is the serial clock i/o pin of csi4. chapter 2 pin functions user?s manual u15905ej2v1ud 38 (3) p30 to p32 (port 3) ? 3-state i/o port 3 is a 3-bit i/o port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, p30 to p32 also operate as the i/o pins of the serial interface. these pins can be set to the port or control mode in 1-bit units. the output mode of p31 and p32 can also be se t to normal output or n-ch open-drain output. (a) port mode p30 to p32 can be set to the input or output mode in 1-bit units by using port mode register 3 (pm3). (b) control mode (i) si1 (serial input 1) ? input this pin inputs the serial receive data of csi1. (ii) so1 (serial output 1) ? output this pin outputs the serial transmit data of csi1. (iii) sck1 (serial clock 1) ? 3-state i/o this is the serial clock i/o pin of csi1. (iv) rxd0 (receive data 0) ? input this pin inputs the serial receive data of uart0. (v) txd0 (transmit data 0) ? output this pin outputs the serial transmit data of uart0. (4) p40 to p46 (port 4) ? 3-state i/o port 4 is a 7-bit i/o port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, p40 to p46 also op erate as the i/o pins of t he timer/counters and serial interface, and as the external interrupt request input pi n. these pins can be set to the port or control mode in 1-bit units. the output mode of p41 and p42 can also be se t to normal output or n-ch open-drain output. (a) port mode p40 to p46 can be set to the input or output mode in 1-bit units by using port mode register 4 (pm4). (b) control mode (i) ti0, ti1 (timer input 0, 1) ? input these pins input an external count clock to timers 0 and 1. (ii) to0, to1 (timer output 0, 1) ? output these pins output a pulse signal from timers 0 and 1. (iii) tclr0, tclr1 (timer clear input 0, 1) ? input these pins input an external clear signal to timers 0 and 1. chapter 2 pin functions user?s manual u15905ej2v1ud 39 (iv) si0 (serial input 0) ? input this pin inputs the serial receive data of csi0. (v) so0 (serial output 0) ? output this pin outputs the serial transmit data of csi0. (vi) sck0 (serial clock 0) ? 3-state i/o this is the serial clock i/o pin of csi0. (vii) sda (serial data) ? i/o this pin inputs/outputs the serial transmit/receive data of i 2 c ( pd703200y, 703201y, 70f3201y, 703204y, and 70f3204y only). (viii) scl (serial clock) ? i/o this pin inputs/outputs the serial clock to/from i 2 c ( pd703200y, 703201y, 70f 3201y, 703204y, and 70f3204y only). (ix) intp00, intp01, intp10, intp11 (interrupt request to timer) ? input these pins input an external interrupt request to timers 0 and 1. (5) p70 to p711 (port 7) (v850es/sa2) ? input p70 to p715 (port 7) (v850es/sa3) ? input [v850es/sa2] port 7 is a 12-bit input port with all its bits fixed to the input mode. besides functioning as input port pins, p70 to p711 also operate as the analog input pins of the a/d converter in the control mode. however, the mode of these pi ns cannot be changed between the input port mode and analog input mode. (a) port mode p70 to p711 function as input port pins. (b) control mode p70 to p711 function as the ani0 to ani11 pins. the mode of these pins cannot be changed between the input port mode and analog input mode. (i) ani0 to ani11 (analog input 0 to 11) ? input these are the analog input pins of the a/d converter. to prevent these pins malfunctioning due to noise, connect a capacitor between these pins and av ss . make sure that a voltage outside the range of av ss to av ref0 is not applied to any pin that is being used as an input pin of the a/d converter. if t here is a possibility that a noise greater than av ref0 or lower than av ss will be superimposed on any of these pins, clamp the pins using a diode with a low v f . chapter 2 pin functions user?s manual u15905ej2v1ud 40 [v850es/sa3] port 7 is a 16-bit input port with all its bits fixed to the input mode. besides functioning as input port pins, p70 to p715 also operate as the analog input pins of the a/d converter in the control mode. however, the mode of these pi ns cannot be changed between the input port mode and analog input mode. (a) port mode p70 to p715 function as input port pins. (b) control mode p70 to p715 function as the ani0 to ani15 pins. the mode of these pins cannot be changed between the input port mode and analog input mode. (i) ani0 to ani15 (analog input 0 to 15) ? input these are the analog input pins of the a/d converter. to prevent these pins malfunctioning due to noise, connect a capacitor between these pins and av ss . make sure that a voltage outside the range of av ss to av ref0 is not applied to any pin that is being used as an input pin of the a/d converter. if t here is a possibility that a noise greater than av ref0 or lower than av ss will be superimposed on any of these pins, clamp the pins using a diode with a low v f . (6) p80, p81 (port 8) ? input/output port 8 is a 2-bit input port. besides functioning as input port pins, p80 and p81 al so operate as the analog output pins of the d/a converter in the control mode. the mode of these pins, however, cannot be changed between the control mode and input port mode. (a) port mode p80 and p81 function as input port pins. (b) control mode (i) ano0, ano1 (analog output 0, 1) ? output these pins are the analog output pins of the d/a converter. chapter 2 pin functions user?s manual u15905ej2v1ud 41 (7) p90 to p915 (port 9) ? 3-state i/o port 9 is a 16-bit i/o port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, p90 to p915 also operat e as the i/o pins of the serial interface and timer/counters, the address bus pins to extend the memory externally, and external interrupt request input pins. these pins can be set to the port or control mode in 1-bit units. the output mode of p911, p912, p914, and p915 can also be set to normal output or n-ch open-drain output. (a) port mode p90 to p915 can be set to the input or output mode in 1-bit units by using port mode register 9 (pm9). (b) control mode (i) si2, si3 (serial input 2, 3) ? input these pins input the serial receive data of csi2 and csi3. (ii) so2, so3 (serial output 2, 3) ? output these pins output the serial transmit data of csi2 and csi3. (iii) sck2, sck3 (serial clock 2, 3) ? 3-state i/o these pins are the serial clock i/o pins of csi2 and csi3. (iv) rxd1 (receive data 1) ? input this pin inputs the serial receive data of uart1. (v) txd1 (transmit data 1) ? output this pin outputs the serial transmit data of uart1. (vi) to2 to to5 (timer output 2 to 5) ? output these pins output a pulse signal from timers 2 to 5. (vii) a0 to a15 (address bus 0 to 15) ? output these pins form a 16-bit address output bus to access an external memory. the output signal changes at the rising edge of the t1 state in the bus cycle. when the bus cycle is not active, they retain the address of the bus cycle immediately before. (viii) intp5, intp6 (interrupt re quest from peripherals) ? input these pins input an external interrupt request. (8) pcd1 to pcd3 (port cd) (v850es/sa3 only) ? 3-state i/o port cd is a 3-bit i/o port that can be set to the input or output mode in 1-bit units. pcd1 to pcd3 can be set to the input or output mode in 1-bit units by using port mode register cd (pmcd). chapter 2 pin functions user?s manual u15905ej2v1ud 42 (9) pcm0 to pcm3 (port cm) (v850es/sa2) ? 3-state i/o pcm0 to pcm5 (port cm) (v850es/sa3) ? 3 state i/o [v850es/sa2] port cm is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, in the control mode pcm0 to pcm3 also operate as the bus hold control signal output and bus clock output pins, and as the contro l signal that inserts a wait state (wait) in the bus cycle. (a) port mode pcm0 to pcm3 can be set to the input or output mode in 1-bit units by using port mode register cm (pmcm). (b) control mode (i) hldak (hold acknowledge) ? output this pin outputs an acknowledge signal indicating that the v850es/sa2 has made the address bus, data bus, and control bus go into a high-impedance state, in response to a bus hold request. while this signal is active, the address bus, data bu s, and control bus are in the high-impedance state. (ii) hldrq (hold request) ? input this pin is used by an external device to request the v850es/sa2 to release the address bus, data bus, and control bus. a signal can be input to this pin asynchronously to clkout. when this pin is active, the v850es/sa2 makes the address bus, data bus, and control bus go into a high-impedance state immediately or after completion of the bus cycle under execution, if any, and then asserts the hldak signal and releases the bus. (iii) clkout (clock output) ? output this pin outputs the internally generated bus clock. (iv) wait (wait) ? input this pin inputs a control sign al that inserts a wait state in the bu s cycle. the signal is sampled at the fall of the clkout signal of the t2 and tw states of the bus cycle in the multiplexed mode, and at the rise of the clkout signal immedi ately after the t1 and tw states of the bus cycle in the separate mode. the wait function is turned on/off by por t mode control register cm (pmccm). chapter 2 pin functions user?s manual u15905ej2v1ud 43 [v850es/sa3] port cm is a 6-bit i/o port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, in the control mode pcm0 to pcm5 also operate as the bus hold control signal output and bus clock output pins, and as the contro l signal that inserts a wait state (wait) in the bus cycle. (a) port mode pcm0 to pcm5 can be set to the input or output mode in 1-bit units by using port mode register cm (pmcm). (b) control mode (i) hldak (hold acknowledge) ? output this pin outputs an acknowledge signal indicating that the v850es/sa3 has made the address bus, data bus, and control bus go into a high-impedance state, in response to a bus hold request. while this signal is active, the address bus, data bu s, and control bus are in the high-impedance state. (ii) hldrq (hold request) ? input this pin is used by an external device to request the v850es/sa3 to release the address bus, data bus, and control bus. a signal can be input to this pin asynchronously to clkout. when this pin is active, the v850es/sa3 makes the address bus, data bus, and control bus go into a high-impedance state immediately or after completion of the bus cycle under execution, if any, and then asserts the hldak signal and releases the bus. (iii) clkout (clock output) ? output this pin outputs the internally generated bus clock. (iv) wait (wait) ? input this pin inputs a control sign al that inserts a wait state in the bu s cycle. the signal is sampled at the fall of the clkout signal of the t2 and tw states of the bus cycle in the multiplexed mode, and at the rise of the clkout signal immedi ately after the t1 and tw states of the bus cycle in the separate mode. the wait function is turned on/off by por t mode control register cm (pmccm). chapter 2 pin functions user?s manual u15905ej2v1ud 44 (10) pcs0 to psc3 (port cs) (v850es/sa2) ? 3-state i/o pcs0 to pcs5 (port cs) (v850es/sa3) ? 3-state i/o [v850es/sa2] port cs is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, in the control m ode pcs0 to psc3 also operate as the control signal output pins when the memory and peripheral i/o are expanded externally. (a) port mode pcs0 to psc3 can be set to the input or output mo de in 1-bit units by using port mode register cm (pmcs). (b) control mode (i) cs0 to cs3 (chip select) ? output these are the chip select signals for the sram, external rom, and external peripheral i/o area. the csn signal is assigned to memory block n (n = 0 to 3). each of these signals is active while the bus cycle accessing the corresponding memory block is being executed, and inactive in the idle state (ti). [v850es/sa3] port cs is an 8-bit i/o port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, in the control m ode pcs0 to psc3 also operate as the control signal output pins when the memory and peripheral i/o are expanded externally. (a) port mode pcs0 to pcs7 can be set to the input or output mode in 1-bit units by using port mode register cs (pmcs). (b) control mode (i) cs0 to cs3 (chip select) ? output these are the chip select signals for the sram, external rom, and external peripheral i/o area. the csn signal is assigned to memory block n (n = 0 to 3). each of these signals is active while the bus cycle accessing the corresponding memory block is being executed, and inactive in the idle state (ti). chapter 2 pin functions user?s manual u15905ej2v1ud 45 (11) pct0, pct1, pct4 to pct7 (port ct) (v850es/sa2) ? 3-state i/o pct0 to pct7 (port ct) (v850es/sa3) ? 3-state i/o [v850es/sa2] port ct is a 6-bit port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, in the control mode pct0, pct1, and pct4 to pct7 also operate as the control signal output pins when the memory is expanded externally. (a) port mode pct0, pct1, and pct4 to pct7 can be set to the in put or output mode in 1-bit units by using port mode register ct (pmct). (b) control mode (i) wr0 (lower byte write strobe) ? output this is the write strobe signal output pin for t he lower data of the external 16-bit data bus. (ii) wr1 (higher byte write strobe) ? output this is the write strobe signal output pin for t he higher data of the external 16-bit data bus. (iii) rd (read strobe) ? output this is the read strobe signal output pin for the external 16-bit data bus. (iv) astb (address strobe) ? output this is the latch strobe signal output pin of the extern al address bus. the output signal goes low at the falling edge of the t1 state in the bus cycle, and goes high at the falling edge of the t3 state. it is high when the bus cycle is not active. [v850es/sa3] port ct is an 8-bit port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins, in the control m ode pct0 to pct7 also operate as the control signal output pins when the memory is expanded externally. (a) port mode pct0 to pct7 can be set to the input or output mode in 1-bit units by using port mode register ct (pmct). (b) control mode (i) wr0 (lower byte write strobe) ? output this is the write strobe signal output pin for t he lower data of the external 16-bit data bus. (ii) wr1 (higher byte write strobe) ? output this is the write strobe signal output pin for t he higher data of the external 16-bit data bus. chapter 2 pin functions user?s manual u15905ej2v1ud 46 (iii) rd (read strobe) ? output this is the read strobe signal output pin for the external 16-bit data bus. (iv) astb (address strobe) ? output this is the latch strobe signal output pin of the extern al address bus. the output signal goes low at the falling edge of the t1 state in the bus cycle, and goes high at the falling edge of the t3 state. it is high when the bus cycle is not active. (12) pdh0 to pdh5 (port dh) (v850es/sa2) ? 3-state i/o pdh0 to pdh7 (port dh) (v850es/sa3) ? 3-state i/o [v850es/sa2] port dh is a 6-bit port that can be set to t he input or output mode in 1-bit units. besides functioning as i/o port pins, in the control mode pdh0 to pdh5 also operate as the address bus pins when the memory is expanded externally. (a) port mode pdh0 to pdh5 can be set to the input or output mode in 1-bit units by using port mode register dh (pmdh). (b) control mode (i) a16 to a21 (address bus 16 to 21) ? output these pins form a 6-bit address output bus to access an external device. the output signal changes at the rising edge of the t1 state in the bus cycle. the address of the immediately preceding bus cycle is retained when the bus cycle is inactive. [v850es/sa3] port dh is an 8-bit port that can be set to t he input or output mode in 1-bit units. besides functioning as i/o port pins, in the control mode pdh0 to pdh7 also operate as the address bus pins when the memory is expanded externally. (a) port mode pdh0 to pdh7 can be set to the input or output mode in 1-bit units by using port mode register dh (pmdh). (b) control mode (i) a16 to a23 (address bus 16 to 23) ? output these pins form an 8-bit address output bus to acce ss an external device. the output signal changes at the rising edge of the t1 state in the bus cycle. the address of the immediately preceding bus cycle is retained when the bus cycle is inactive. chapter 2 pin functions user?s manual u15905ej2v1ud 47 (13) pdl0 to pdl15 (port dl) ? 3-state i/o port dl is a 16-bit i/o port that can be set to the input or output mode in 1-bit units. besides functioning as i/o port pins , pdl0 to pdl15 also operate a time -division address/data bus (ad0 to ad15) when the memory is externally expanded. each bit of the port can be individually set to the port or control mode. in addition, the pdl5 pin of the pd70f3201, 70f3201y, 70f3204, and 70f 3204y functions as the flmd1 pin when the flash memory is programmed (when a high level is input to flmd0). at this time, be sure to input a low level to the flmd1 pin. (a) port mode pdl0 to pdl15 can be set to the input or output mode in 1-bit units by using port mode register dl (pmdl). (b) control mode (i) ad0 to ad15 (address/data bus 0 to 15) ? 3-state i/o this is a multiplexed address/data bus that is used to access an external device. in the multiplexed bus mode, it outputs an address or inputs/outputs data . in the separate bus mode, the bus inputs or outputs data. (14) reset (reset) ? input the reset signal is input asynchronously. if a signal havi ng a specific low-level width is input to this pin, regardless of the operation clock, the system is reset as a priority over all other operations. this pin is used to release the standby mode (halt, idle, or stop) as well as for normal initialization/starting. (15) x1, x2 (crystal for main clock) connect an oscillator for system cl ock generation to these pins. (16) xt1, xt2 (crystal for subclock) connect an oscillator for subclock generation to these pins. (17) av dd (analog v dd ) this pin supplies positive power to the a/d converter and alternate-function port pins. (18) av ss (analog v ss ) this is a ground pin for the a/d converter and alternate-function port pins. (19) av ref0 (analog reference voltage) ? input this pin supplies a reference voltage to the a/d converter. (20) av ref1 (analog reference voltage) ? input this pin supplies a reference voltage to the d/a converter. chapter 2 pin functions user?s manual u15905ej2v1ud 48 (21) ev dd (power supply for port) this pin supplies positive power for the i/o ports and pins with alternate functions. (22) ev ss (ground for port) this is a ground pin for the i/o ports and pins with alternate functions. (23) v dd (power supply) this pin supplies positive power. connect all the v dd pins to the positive power supply. (24) v ss (ground) this is the ground pin. connect all the v ss pins to ground. (25) flmd0, flmd1 (flash programming mode) these pins supply positive power for flash memory programming mode. these pins are provided only in the pd70f3201, 70f3201y, 70f3204, and 70f3204y. in the normal operation mode, connect these pins to v ss . (26) ic (internally connected) these pins are internally connected and provided only in the pd703200, 703200y, 70f3201, 70f3201y, 70f3204, and 70f3204y. in the normal operation mode, connect these pins to v ss . chapter 2 pin functions user?s manual u15905ej2v1ud 49 2.4 types of pin i/o circuits, i/o buffer po wer supplies, and connection of unused pins (1/2) pin alternate function i/o circuit type recommended connection p00 nmi p01 to p04 intp0/ti2 to intp3/ti5 p05 intp4 5-w [p20] [si4] 5-w [p21] [so4] 10-e [p22] [sck4] 10-f p30 si1/rxd0 5-w p31 so1/txd0 10-e p32 sck1 10-f p40 si0 5-w p41 so0/sda note 10-f p42 sck0/scl note 10-f p43 intp00/ti0/tclr0 p44 intp01/to0 p45 intp10/ti1/tclr1 p46 intp11/to1 5-w input: independently connect to ev dd or ev ss via a resistor. output: leave open. p70 to p711, [p712 to p715] ani0 to ani11 [ani12 to ani15] 9 p80, p81 ano0, ano1 34 independently connect to av dd or av ss via a resistor. p90, p91 a0, a1 5-a p92, p93 a2/intp5, a3/intp6 5-w p94 to p97 a4/to2 to a7/to5 5-a p98 a8/rxd1 5-w p99 a9/txd1 5-a p910 a10/si2 5-w p911 a11/so2 10-e p912 a12/sck2 10-f p913 a13/si3 5-w p914 a14/so3 10-e p915 a15/sck3 10-f [pcd1 to pcd3] ? pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq [pcm4] ? [pcm5] ? 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. note pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only remark [ ]: pins provided only in the v850es/sa3 chapter 2 pin functions user?s manual u15905ej2v1ud 50 (2/2) pin alternate function i/o circuit type recommended connection pcs0 to pcs3 cs0 to cs3 [pcs4 to pcs7] ? pct0, pct1 wr0, wr1 [pct2, pct3] ? pct4 rd pct5 ? pct6 astb pct7 ? pdh0 to pdh5, [pdh6, pdh7] a16 to a21, [a22, a23] pdl0 to pdl4 ad0 to ad4 pdl5 ad5/flmd1 note 1 pdl6 to pdl15 ad6 to ad15 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. av dd ? ? ? av ref0 ? ? connect to av ss via a resistor. av ref1 ? ? connect to av ss via a resistor. av ss ? ? ? ev dd ? ? ? ev ss ? ? ? flmd0 note 1 ? ? connect to v ss . ic note 2 ? ? ? reset ? 2 ? v dd ? ? ? v ss ? ? ? x1 ? ? ? x2 ? ? ? xt1 ? 16 connect to v ss via a resistor. xt2 ? 16 leave open. notes 1. pd70f3201, 70f3201y, 70f3204, and 70f3204y only 2. pd703200, 703200y, 703201, 703201y, 703204, and 703204y only remark [ ]: pins provided only in the v850es/sa3 chapter 2 pin functions user?s manual u15905ej2v1ud 51 figure 2-1. pin i/o circuits (1/2) type 2 schmitt-triggered input with hysteresis characteristics. type 5 type 5-w in data output disable p-ch in/out ev dd n-ch input enable data output disable p-ch in/out ev dd n-ch input enable p-ch ev dd pull-up enable type 5-a data output disable p-ch in/out ev dd n-ch input enable input enable p-ch ev dd pull-up enable type 9 in comparator + ? av ref0 (threshold voltage) p-ch n-ch input enable type 10-e data output disable p-ch in/out ev dd n-ch p-ch ev dd pull-up enable open drain chapter 2 pin functions user?s manual u15905ej2v1ud 52 figure 2-1. pin i/o circuits (2/2) type 10-f type 16 p-ch feedback cut-off xt1 xt2 data output disable open drain p-ch in/out ev dd n-ch p-ch ev dd pull-up enable input enable type 34 in/out p-ch n-ch input enable analog output voltage user?s manual u15905ej2v1ud 53 chapter 3 cpu function the cpu of the v850es/sa2 and v850es/sa3 is based on risc architecture and executes almost all instructions in one clock by using a 5-stage pipeline. 3.1 features minimum instruction execution time: 50 ns: main clock = 20 mhz ( pd703200, 703201, 703204, 70f3201, 70f3204) 59 ns: main clock = 17 mhz ( pd703200y, 703201y, 703204y, 70f3201y, 70f3204y) 30.5 s: subclock = 32.768 khz memory space program space: 64 mb linear data space: 4 gb linear ? memory block division function: 2, 2, 4, 8 mb/total: 4 blocks general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 chapter 3 cpu function user?s manual u15905ej2v1ud 54 3.2 cpu register set the registers of the v850es/sa2 and v850es/sa3 can be classified into two types: general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) chapter 3 cpu function user?s manual u15905ej2v1ud 55 3.2.1 program register set the program registers include general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a base pointer when these in structions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. when using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time os. if the real-time os does not use r2, it can be used as a register for variables. table 3-1. program registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as work ing register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that i ndicates the beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when t he compiler calls a function pc program counter holds the instruction address during program execution (2) program counter (pc) the program counter holds the instructi on address during program execution. the lower 32 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that execution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h chapter 3 cpu function user?s manual u15905ej2v1ud 56 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/sto re instructions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) note 1 3 nmi status saving register (fepsw) note 1 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 19 exception/debug trap status saving register (dbpsw) note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function expansion (operation is not guaranteed if these registers are accessed) notes 1. because only one set of this register is available, t he contents of this register must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only wh en the dbtrap instruction is executed. caution even if eipc or fepc, or bit 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti instruction after interrupt ser vicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited chapter 3 cpu function user?s manual u15905ej2v1ud 57 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, th e contents of the program counter (pc) are saved to eipc, and the contents of the program status word ( psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and f epsw) if a non-maskable interrupt occurs). the address of the instruction next to the one of the instruction under exec ution, except some instructions, is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved for future function expansion (these bits are always fixed to 0). 31 0 eipc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function user?s manual u15905ej2v1ud 58 (2) nmi status saving registers (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of the program counter (pc) are saved to fepc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to the one of the instruction under exec ution, except some instructions, is saved to fepc when an nmi occurs. the current contents of t he psw are saved to fepsw. because only one set of nmi status saving registers is avai lable, the contents of thes e registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served for future function expansion (these bits are always fixed to 0). 31 0 fepc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (3) interrupt source register (ecr) the interrupt source register (ecr) hol ds the source of an exception or in terrupt if an exception or interrupt occurs. this register holds the exception code of each interrupt source. because this register is a read-only register, data cannot be written to this register using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt chapter 3 cpu function user?s manual u15905ej2v1ud 59 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate th e status of the program (result of instruction execution) and the status of the cpu. if the contents of a bit of this regi ster are changed by using the ldsr instruction, the new contents are validated immediately after completion of ldsr instructi on execution. if the id flag is set to 1, however, interrupt request acknowledgment is disabled even while the ldsr instruction is being executed. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being proces sed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled (ei) 1: interrupt disabled (di) 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. th is flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a ca rry or a borrow occurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page. chapter 3 cpu function user?s manual u15905ej2v1ud 60 note the result of the operation that has performed satura tion processing is determined by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded. 1 1 0 7fffffffh maximum negative value is exceeded. 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execution status saving registers. when the callt instruction is execut ed, the contents of the program count er (pc) are saved to ctpc, and those of the program status wo rd (psw) are saved to ctpsw. the contents saved to ctpc are the address of the inst ruction next to callt. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function user?s manual u15905ej2v1ud 61 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of the instruction next to the one that is executed when an exception trap or debug trap occurs. the current contents of t he psw are saved to dbpsw. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). 31 0 dbpc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a table address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 chapter 3 cpu function user?s manual u15905ej2v1ud 62 3.3 operation modes the v850es/sa2 and v850es/sa3 have the following operation modes. (1) single-chip mode in this mode, each pin related to the bus interface is set to the port mode after system reset has been released. execution branches to the reset entry address of the inte rnal rom, and then instruction processing is started. by setting the pmcdh, pmcdl, pmccm, pmccs, and pmcct registers to the control mode by software, an external device can be connected to the external memory area. (2) flash memory programming mode ( pd70f3201, 70f3201y, 70f3204, and 70f3204y) in this mode, the internal flash memory can be programmed by using a flash programmer. chapter 3 cpu function user?s manual u15905ej2v1ud 63 3.4 address space 3.4.1 cpu address space the cpu of the v850es/sa2 and v850es/sa3 has 32-bit archit ecture and supports up to 4 gb of linear address space (data space) for operand addressing (data access). it also supports up to 64 mb of linear address space (program space) for instruction addressing. note, however, that both the program and data spaces have areas that are prohibited from being used. for details, refer to figure 3-2 . figure 3-1 shows the cpu address space. figure 3-1. cpu address space data area (4 gb linear) program area (64 mb linear) cpu address space ffffffffh 04000000h 00000000h 03ffffffh chapter 3 cpu function user?s manual u15905ej2v1ud 64 3.4.2 image for instruction addressing, up to 16 mb of linear addre ss space (program space) and an internal ram area are supported. up to 4 gb of linear address space (data s pace) is supported for operand addressing (data access). in the 4 gb address space, it seems that t here are sixty-four 64 mb physical addre ss spaces. this means that the same 64 mb physical address space is accessed, regardless of the values of bits 31 to 26. figure 3-2. image on address space program space internal ram area use prohibited area use prohibited area external memory area internal rom area (external memory area) data space image 63 image 1 image 0 internal peripheral i/o area internal ram area use prohibited area external memory area internal rom area (external memory area) 16 mb 4 gb 64 mb 64 mb chapter 3 cpu function user?s manual u15905ej2v1ud 65 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the lowest address of the program space, 00000000h, and the highest addres s, 03ffffffh, are contiguous addresses. that the lo west address and the highest address of the program space are contiguous in this way is called wrap-around. caution because the 4 kb area of addresses 03fff000h to 03ffffffh is an internal peripheral i/o area, instructions cannot be fetc hed from this area. therefore , do not execute an operation in which the result of a branch addr ess calculation affects this area. program space program space (+) direction ( ? ) direction 03fffffeh 03ffffffh 00000000h 00000001h (2) data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the lowest address of the data space, 00000000h, and the highest address, ffffffffh, are contiguous, and wrap-around occurs at the boundary of these addresses. data space data space (+) direction ( ? ) direction fffffffeh ffffffffh 00000000h 00000001h chapter 3 cpu function user?s manual u15905ej2v1ud 66 3.4.4 memory map the v850es/sa2 and v850es/sa3 reserve the areas shown in figure 3-3. figure 3-3. data memory map (physical addresses) (80 kb) use prohibited external memory area note 1 (8 mb) internal rom area note 2 (1 mb) external memory area (1 mb) internal ram area (16 kb) internal peripheral i/o area (4 kb) use prohibited external memory area (4 mb) external memory area (2 mb) (2 mb) cs0 cs1 cs2 cs3 3ffffffh 3fec000h 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 3febfffh 3ffffffh 3fff000h 3ffefffh 3ffb000h 3ffafffh 3fec000h 01fffffh 0100000h 00fffffh 0000000h notes 1. this is the 4 mb space of 0800000h to 0b fffffh in the v850es/sa2 (t he area of 0c00000h to 0ffffffh is the image of 0800000h to 0bfffffh). 2. fetch access and read access to addresses 000 0000h to 00fffffh is made to the internal rom area. however, data write access to these addresses is made to the external memory area. chapter 3 cpu function user?s manual u15905ej2v1ud 67 figure 3-4. program memory map internal ram area (16 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area note (8 mb) external memory area (4 mb) external memory area (1 mb) external memory area (2 mb) internal rom area (1 mb) cs0 cs1 cs2 cs3 03ffffffh 03fff000h 03ffefffh 3ffb000h 3feafffh 01000000h 00ffffffh 00800000h 007fffffh 00400000h 003fffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h note this is the 4 mb space of 0800000h to 0bfffffh in the v850es/sa2 (the area of 0c00000h to 0ffffffh is the image of 0800000h to 0bfffffh). remark instructions can be executed to the external me mory area without execution branching from the internal rom area to the external memory area. chapter 3 cpu function user?s manual u15905ej2v1ud 68 3.4.5 areas (1) internal rom area (a) memory map 1 mb of addresses 0000000h to 00fffffh is reserved as the internal rom area. <1> pd703200 and 703200y 128 kb are allocated to the following addresses as the internal physical rom (mask rom). ? addresses 0000000h to 001ffffh figure 3-5. internal rom area (128 kb) access prohibited area internal rom 0020000h 00fffffh 0000000h 001ffffh <2> pd703201, 703201y, 703204, and 703204y 256 kb are allocated to the following addresses as the internal physical rom (mask rom). ? 0000000h to 003ffffh <3> pd70f3201, 70f3201y, 70f3204, and 70f3204y 256 kb are allocated to the following addresses as the internal physical rom (flash memory). ? 0000000h to 003ffffh chapter 3 cpu function user?s manual u15905ej2v1ud 69 figure 3-6. internal rom/intern al flash memory area (256 kb) access prohibited area internal rom/ internal flash memory 0040000h 00fffffh 0000000h 003ffffh chapter 3 cpu function user?s manual u15905ej2v1ud 70 ? interrupt/exception table the v850es/sa2 and v850es/sa3 speed up the interrupt response time by fixing handler addresses corresponding to inte rrupts/exceptions. a collection of these handler addresses is called an interr upt/exception table, which is mapped to the internal rom area. when an interrupt/exception is acknowledged, execution jumps to a handler address and the program in the area starting from that address is ex ecuted. table 3-3 shows the interrupt/exception sources and corresponding addresses. table 3-3. interrupt/exception table first address of interrupt/exception table interrupt/exception source first address of interrupt/exception table interrupt/exception source 00000000h reset 00000180h inttm3 00000010h nmi 00000190h inttm4 00000020h intwdt 000001a0h inttm5 00000040h trap0n (n = 0 to f) 000001b0h intcsi0 00000050h trap1n (n = 0 to f) 000001c0h intiic note 1 00000060h ilgop/dbg0 000001d0h intcsi1 00000080h intwdtm 000001e0h intsre0 00000090h intp0 000001f0h intsr0 000000a0h intp1 00000200h intst0 000000b0h intp2 00000210h intcsi2 000000c0h intp3 00000220h intsre1 000000d0h intp4 00000230h intsr1 000000e0h intp5 00000240h intst1 000000f0h intp6 00000250h intcsi3 00000100h intrtc 00000260h intcsi4 note 2 00000110h intcc00 00000270h intad 00000120h intcc01 00000280h intdma0 00000130h intovf0 00000290h intdma1 00000140h intcc10 000002a0h intdma2 00000150h intcc11 000002b0h intdma3 00000160h intovf1 000002c0h introv 00000170h inttm2 000002d0h intbrg notes 1. pd703200y, 703201, 703204, 70f3201y, and 70f3204y only 2. v850es/sa3 only chapter 3 cpu function user?s manual u15905ej2v1ud 71 (2) internal ram area 60 kb of addresses 3ff0000h to 3ffefffh ar e reserved as the internal ram area. <1> pd703200 and 703200y 8 kb are allocated to the following addresses as the internal physical ram. ? 3ffd000h to 3ffefffh figure 3-7. internal ram area (8 kb) internal ram (8 kb) access prohibited area 3ffd000h 3ff0000h 3ffefffh 3ffcfffh <2> pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, and 70f3204y 16 kb are allocated to the following addresses as the internal physical ram. ? 3ffb000h to 3ffefffh figure 3-8. internal ram area (16 kb) internal ram area (16 kb) access prohibited area 3ffb000h 3ffefffh 3ff0000h 3ffafffh chapter 3 cpu function user?s manual u15905ej2v1ud 72 (3) internal peripheral i/o area 4 kb of addresses 3fff000h to 3ffffffh are allo cated as the internal peripheral i/o area. figure 3-9. internal peripheral i/o area internal peripheral i/o area (4 kb) 3ffffffh 3fff000h peripheral i/o registers that have functions to specif y the operation mode for and monitor the status of the internal peripheral i/o are mapped to the internal peripheral i/o area. pr ogram cannot be fetched from this area. cautions 1. when a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read , and data is written to the lower 8 bits. 3. addresses not defined as registers are r eserved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. (4) external memory area 15 mb (0100000h to 0ffffffh) are a llocated as the external memory area. for details, refer to chapter 5 bus control function . chapter 3 cpu function user?s manual u15905ej2v1ud 73 3.4.6 recommended use of address space the architecture of the v850e s/sa2 and v850es/sa3 requires that a regist er that serves as a pointer be secured for address generation when operand data in the data sp ace is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data . because the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose r egisters as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the program counter (p c), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb spac e of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the program space, access addresses 3ffc000h to 3ffefffh. (2) data space with the v850es/sa2 and v850es/sa3, it seems that there are sixty-four 64 mb address spaces on the 4 gb cpu address space. therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) application example of wrap-around if r = r0 (zero register) is specified for the ld/st di sp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources of the internal hardware can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically eliminates the need for registers dedicated to pointers. figure 3-10. application example of wrap-around (v850e/sa3) internal rom area internal peripheral i/o area access prohibited area internal ram area 3 2 kb 4 kb 16 kb 12 kb (r = ) 0003ffffh 00007fffh 00000000h fffff000h ffffefffh ffffb000h ffffafffh ffff8000h chapter 3 cpu function user?s manual u15905ej2v1ud 74 figure 3-11. recommended memory map ffffffffh fffff000h ffffefffh ffffc000h ffffbfffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ffb000h 03ffafffh 03fec000h 03febfffh 01000000h 00ffffffh 01000000h 000fffffh 00040000h 0003ffffh 00000000h xfffffffh xffff000h xfffefffh xfffb000h xfffafffh xffec000h xffebfffh x0100000h x00fffffh x0000000h internal peripheral i/o internal rom internal ram external memory use prohibited data space program space internal peripheral i/o internal ram external memory use prohibited internal ram internal peripheral i/o note internal rom internal rom program space, 64 mb note access to this area is prohibited. to access the internal i/o in th is area, specify addresses ffff000h to fffffffh. remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd703204. chapter 3 cpu function user?s manual u15905ej2v1ud 75 3.4.7 peripheral i/o registers (1/8) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port register dl pdl fffff004h port register dll pdll fffff005h port register dlh pdlh fffff006h port register dh pdh fffff008h port register cs pcs fffff00ah port register ct pct fffff00ch port register cm pcm fffff00eh port register cd note pcd undefined fffff024h port mode register dl pmdl ffffh fffff024h port mode register dll pmdll fffff025h port mode register dlh pmdlh fffff026h port mode register dh pmdh fffff028h port mode register cs pmcs fffff02ah port mode register ct pmct fffff02ch port mode register cm pmcm fffff02eh port mode register cd note pmcd ffh fffff044h port mode control register dl pmcdl 0000h fffff044h port mode control register dll pmcdll fffff045h port mode control register dlh pmcdlh fffff046h port mode control register dh pmcdh fffff048h port mode control register cs pmccs fffff04ah port mode control register ct pmcct fffff04ch port mode control register cm pmccm 00h fffff066h bus size configuration register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l fffff082h dma source address register 0h dsa0h fffff084h dma destination address register 0l dda0l fffff086h dma destination address register 0h dda0h fffff088h dma source address register 1l dsa1l fffff08ah dma source address register 1h dsa1h fffff08ch dma destination address register 1l dda1l fffff08eh dma destination address register 1h dda1h fffff090h dma source address register 2l dsa2l fffff092h dma source address register 2h dsa2h fffff094h dma destination address register 2l dda2l fffff096h dma destination address register 2h dda2h fffff098h dma source address register 3l dsa3l fffff09ah dma source address register 3h dsa3h fffff09ch dma destination address register 3l dda3l fffff09eh dma destination address register 3h dda3h r/w undefined note v850es/sa3 only chapter 3 cpu function user?s manual u15905ej2v1ud 76 (2/8) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff0c0h dma transfer count register 0 dbc0 fffff0c2h dma transfer count register 1 dbc1 fffff0c4h dma transfer count register 2 dbc2 fffff0c6h dma transfer count register 3 dbc3 undefined fffff0d0h dma addressing control register 0 dadc0 fffff0d2h dma addressing control register 1 dadc1 fffff0d4h dma addressing control register 2 dadc2 fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 fffff0e2h dma channel control register 1 dchc1 fffff0e4h dma channel control register 2 dchc2 fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff110h interrupt control register wdtic fffff112h interrupt control register pic0 fffff114h interrupt control register pic1 fffff116h interrupt control register pic2 fffff118h interrupt control register pic3 fffff11ah interrupt control register pic4 fffff11ch interrupt control register pic5 fffff11eh interrupt control register pic6 fffff120h interrupt control register rtcic fffff122h interrupt control register ccic00 fffff124h interrupt control register ccic01 fffff126h interrupt control register ovfic0 fffff128h interrupt control register ccic10 fffff12ah interrupt control register ccic11 fffff12ch interrupt control register ovfic1 fffff12eh interrupt control register tmic2 fffff130h interrupt control register tmic3 fffff132h interrupt control register tmic4 fffff134h interrupt control register tmic5 fffff136h interrupt control register csiic0 fffff138h interrupt control register note iicic r/w 47h note pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only chapter 3 cpu function user?s manual u15905ej2v1ud 77 (3/8) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff13ah interrupt control register csiic1 fffff13ch interrupt control register sreic0 fffff13eh interrupt control register sric0 fffff140h interrupt control register stic0 fffff142h interrupt control register csiic2 fffff144h interrupt control register sreic1 fffff146h interrupt control register sric1 fffff148h interrupt control register stic1 fffff14ah interrupt control register csiic3 fffff14ch interrupt control register note csiic4 fffff14eh interrupt control register adic fffff150h interrupt control register dmaic0 fffff1 52 h interrupt control register dmaic1 fffff1 54 h interrupt control register dmaic2 fffff1 56 h interrupt control register dmaic3 fffff1 58 h interrupt control register rovic fffff1 5a h interrupt control register brgic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc fffff200h a/d converter mode register adm fffff201h analog input channel specification register ads fffff202h power fail comparison mode register pfm fffff203h power fail comparison threshold value register pft r/w 00h fffff204h a/d conversion result register adcr fffff205h a/d conversion result register h adcrh r undefined fffff280h d/a converter conversion value setting register 0 dacs0 fffff282h d/a converter conversion value setting register 1 dacs1 fffff288h d/a converter mode register dam 00h fffff400h port register 0 p0 fffff404h port register 2 note p2 fffff406h port register 3 p3 fffff408h port register 4 p4 r/w fffff40eh port register 7 p7 fffff40eh port register 7l p7l fffff40fh port register 7h p7h fffff410h port register 8 p8 r fffff412h port register 9 p9 fffff412h port register 9l p9l fffff413h port register 9h p9h r/w undefined note v850es/sa3 only chapter 3 cpu function user?s manual u15905ej2v1ud 78 (4/8) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff420h port mode register 0 pm0 fffff424h port mode register 2 note pm2 fffff426h port mode register 3 pm3 fffff428h port mode register 4 pm4 ffh fffff432h port mode register 9 pm9 ffffh fffff432h port mode register 9l pm9l fffff433h port mode register 9h pm9h ffh fffff440h port mode control register 0 pmc0 fffff444h port mode control register 2 note pmc2 fffff446h port mode control register 3 pmc3 fffff448h port mode control register 4 pmc4 00h fffff452h port mode control register 9 pmc9 0000h fffff452h port mode control register 9l pmc9l fffff453h port mode control register 9h pmc9h fffff466h port function control register 3 pfc3 fffff468h port function control register 4 pfc4 00h fffff472h port function control register 9 pfc9 0000h fffff472h port function control register 9l pfc9l fffff473h port function control register 9h pfc9h 00h fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc r/w aaaah fffff600h timer 0 tm0 r fffff602h capture/compare register 00 cc00 fffff604h capture/compare register 01 cc01 0000h fffff606h timer control register 00 tmc00 00h fffff608h timer control register 01 tmc01 20h fffff609h valid edge select register 0 ses0 r/w 00h fffff610h timer 1 tm1 r fffff612h capture/compare register 10 cc10 fffff614h capture/compare register 11 cc11 0000h fffff616h timer control register 10 tmc10 00h fffff618h timer control register 11 tmc11 20h fffff619h valid edge select register 1 ses1 r/w 00h fffff640h timer counter 23 tm23 0000h fffff640h timer counter 2 tm2 fffff641h timer counter 3 tm3 r 00h fffff642h compare register 23 cr23 0000h fffff642h compare register 2 cr2 fffff643h compare register 3 cr3 r/w 00h note v850es/sa3 only chapter 3 cpu function user?s manual u15905ej2v1ud 79 (5/8) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff644h timer clock selection register 23 tcl23 0000h fffff644h timer clock selection register 2 tcl2 fffff645h timer clock selection register 3 tcl3 00h fffff646h timer mode control register 23 tmc23 0000h fffff646h timer mode control register 2 tmc2 fffff647h timer mode control register 3 tmc3 r/w 00h fffff650h timer counter 45 tm45 0000h fffff650h timer counter 4 tm4 fffff651h timer counter 5 tm5 r 00h fffff652h compare register 45 cr45 0000h fffff652h compare register 4 cr4 fffff653h compare register 5 cr5 00h fffff654h timer clock selection register 45 tcl45 0000h fffff654h timer clock selection register 4 tcl4 fffff655h timer clock selection register 5 tcl5 00h fffff656h timer mode control register 45 tmc45 0000h fffff656h timer mode control register 4 tmc4 fffff657h timer mode control register 5 tmc5 00h fffff6c0h oscillation stabilization time selection register osts 04h fffff6c1h watchdog timer clock se lection register wdcs fffff6c2h watchdog timer mode register wdtm 00h fffff6e0h rtc operation control register rtcc 808xh fffff6e0h rtc operation control register 0 rtcc0 80h fffff6e1h rtc operation control register 1 rtcc1 r/w 8xh fffff6e2h sub-count register subc xxxxh fffff6e2h sub-count register l subcl fffff6e3h sub-count register h subch xxh fffff6e4h minute/second count register secmin xxxxh fffff6e4h second count register sec fffff6e5h minute count register min xxh fffff6e6h day/hour count register hourday 0xxxh fffff6e6h hour count register hour xxh fffff6e7h day count register day 0xh fffff6e8h week count register week 0xxxh fffff6e8h week count register l weekl xxh fffff6e9h week count register h weekh r 0xh fffff6eah minute/second count setting register secminb 0000h fffff6eah second count setting register secb fffff6ebh minute count setting register minb 00h fffff6ech day/hour count setting register hourdayb 0000h fffff6ech hour count setting register hourb fffff6edh day count setting register dayb w 00h chapter 3 cpu function user?s manual u15905ej2v1ud 80 (6/8) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffff6eeh week count setting register weekb 0000h fffff6eeh week count setting register l weekbl fffff6efh week count setting register h weekbh w fffff802h system status register sys 00h fffff810h dma trigger factor register 0 dtfr0 fffff812h dma trigger factor register 1 dtfr1 fffff814h dma trigger factor register 2 dtfr2 fffff816h dma trigger factor register 3 dtfr3 fffff820h power save mode register psmr 00h fffff828h processor clock control register pcc 03h fffff840h correction address register 0 corad0 00000000h fffff840h correction address register 0l corad0l fffff842h correction address register 0h corad0h 0000h fffff844h correction address register 1 corad1 00000000h fffff844h correction address register 1l corad1l fffff846h correction address register 1h corad1h 0000h fffff848h correction address register 2 corad2 00000000h fffff848h correction address register 2l corad2l fffff84ah correction address register 2h corad2h 0000h fffff84ch correction address register 3 corad3 00000000h fffff84ch correction address register 3l corad3l fffff84eh correction address register 3h corad3h 0000h fffff880h correction control register corcn fffff8b0h prescaler mode register prsm fffff8b1h prescaler compare register prscm 00h fffffa00h uart0 operation mode register asim0 r/w 01h fffffa02h receive buffer register 0 rxb0 ffh fffffa03h uart0 reception error status register asis0 r 00h fffffa04h transmit buffer register 0 txb0 r/w ffh fffffa05h uart0 transmit status register asif0 r fffffa06h clock select register 0 cksr0 00h fffffa07h baud rate generator compare register 0 brgc0 ffh fffffa10h uart1 operation mode register asim1 r/w 01h fffffa12h receive buffer register 1 rxb1 ffh fffffa13h uart1 reception error status register asis1 r 00h fffffa14h transmit buffer register 1 txb1 r/w ffh fffffa15h uart1 transmit status register asif1 r fffffa16h clock select register 1 cksr1 00h fffffa17h baud rate generator compare register 1 brgc1 r/w ffh chapter 3 cpu function user?s manual u15905ej2v1ud 81 (7/8) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc12h external interrupt falling edge specification register 9 intf9 0000h fffffc12h external interrupt falling edge specification register 9l intf9l fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc32h external interrupt rising edge specification register 9 intr9 0000h fffffc32h external interrupt rising edge specification register 9l intr9l fffffc40h pull-up resistor option register 0 pu0 fffffc44h pull-up resistor option register 2 note pu2 fffffc46h pull-up resistor option register 3 pu3 fffffc48h pull-up resistor option register 4 pu4 00h fffffc52h pull-up resistor option register 9 pu9 0000h fffffc52h pull-up resistor option register 9l pu9l fffffc53h pull-up resistor option register 9h pu9h fffffc64h port function register 2 note pf2 fffffc66h port function register 3 pf3 fffffc68h port function register 4 pf4 00h fffffc72h port function register 9 pf9 0000h fffffc73h port function register 9h pf9h fffffd00h clocked serial inte rface mode register 0 csim0 fffffd01h clocked serial interface clock selection register 0 csic0 r/w fffffd02h serial i/o shift register 0 sio0 fffffd03h receive-only serial i/o shift register 0 sioe0 r fffffd04h clocked serial interface transmit buffer register 0 sotb0 fffffd10h clocked serial inte rface mode register 1 csim1 fffffd11h clocked serial interface clock selection register 1 csic1 r/w fffffd12h serial i/o shift register 1 sio1 fffffd13h receive-only serial i/o shift register 1 sioe1 r fffffd14h clocked serial interface transmit buffer register 1 sotb1 fffffd20h clocked serial inte rface mode register 2 csim2 fffffd21h clocked serial interface clock selection register 2 csic2 r/w fffffd22h serial i/o shift register 2 sio2 fffffd23h receive-only serial i/o shift register 2 sioe2 r fffffd24h clocked serial interface transmit buffer register 2 sotb2 fffffd30h clocked serial inte rface mode register 3 csim3 fffffd31h clocked serial interface clock selection register 3 csic3 r/w fffffd32h serial i/o shift register 3 sio3 fffffd33h receive-only serial i/o shift register 3 sioe3 r fffffd34h clocked serial interface transmit buffer register 3 sotb3 fffffd40h clocked serial interface mode register 4 note csim4 fffffd41h clocked serial interf ace clock selection register 4 note csic4 r/w fffffd42h serial i/o shift register 4 note sio4 fffffd43h receive-only serial i/o shift register 4 note sioe4 r 00h note v850es/sa3 only chapter 3 cpu function user?s manual u15905ej2v1ud 82 (8/8) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffd44h clocked serial interface transmit buffer register 4 note 1 sotb4 fffffd80h iic shift register note 2 iic fffffd82h iic control register note 2 iicc fffffd83h slave address register note 2 sva fffffd84h iic clock select register note 2 iiccl fffffd85h iic function expansion register note 2 iicx r/w fffffd86h iic status register note 2 iics r ffffffbeh external bus interface mode control register eximc r/w 00h notes 1. v850es/sa3 only 2. pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only chapter 3 cpu function user?s manual u15905ej2v1ud 83 3.4.8 special registers special registers are registers that ar e protected from being written with illegal data due to a program hang-up. the v850es/sa2 and v850es/sa3 have the following three special registers. ? power save control register (psc) ? processor clock control register (pcc) ? watchdog timer mode register (wdtm) in addition, a command register (prcdm) is provided to pr otect against a write access to the special registers so that the application system d oes not inadvertently stop due to a progra m hang-up. a write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the s ystem status register (sys). chapter 3 cpu function user?s manual u15905ej2v1ud 84 (1) setting data to special registers set data to the special registers in the following sequence: <1> store the dma transfer state. <2> disable dma operation. <3> prepare data to be set to the special register in a general-purpose register. <4> write the data prepared in <3 > to the command register (prcmd). <5> write the setting data to the special re gister (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <6> insert nop instructions (5 instructions). <7> check if dma transfer has ended between <1> and <2> above. <8> if dma transfer has not ended and dma op eration is required, enable dma operation. [example] with psc register st.b r11, psmr[r0] ; set psmr register. <1> ld.b dchcn[r0], r12 ; store dma transfer state. andi 0xfe, r12, r13 ; <2> st.b r13 , dchcn [r0] ; disable dma operation. <3> mov 0x02 , r10 <4> st.b r10 , prcmd [r0] ; write prcmd register. <5> st.b r10 , psc [r0] ; set psc register. <6> nop ; dummy instruction nop ; dummy instruction nop ; dummy instruction nop ; dummy instruction nop ; dummy instruction <7> tst1 7, dchcn[r0] ; check if dma transfer has ended between <1> and <2>. bne next ; <8> st.b r12 , dchcn [r0] ; return dma to the original state. next : (next instruction) there is no special sequence to read a special register. cautions 1. when a store instruction is executed to store data in the command register, an interrupt is not acknowledged. this is because it is assumed that steps <4> and <5> above are performed by successive store instructions. if another instruction is placed between <4> and <5>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. although dummy data is written to th e prcmd register, use the same general-purpose register used to set the speci al register (<5> in example) to write data to the prcmd register (<4> in example). the same applies when a general-purpose register is used for addressing. chapter 3 cpu function user?s manual u15905ej2v1ud 85 cautions 3. five nop instructions or more must be inserted immediately after setting the idle mode or software stop mode (by setting the stp bit of the psc register to 1). nop instructions are not necessary in other cases. 4. finish all dma transfers befo re performing the above processing. (2) command register (prcmd) the command register (prcmd) is an 8- bit register that protects the regi sters that may seriously affect the application system from being written, so that the syst em does not inadvertently stop due to a program hang- up. the first write access to a special register (power save control register (psc)) is valid after data has been written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch chapter 3 cpu function user?s manual u15905ej2v1ud 86 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. 0 protection error did not occur. protection error occurred. prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <5> is executed without executing <4> in 3.4.8 (1) setting special register ) (ii) when data is written to a peri pheral i/o register other t han a special register (i ncluding execution of a bit manipulation instruction) after writi ng data to the prcmd register (if <5> in 3.4.8 (1) setting special register is not the setting of a special register) remark if a peripheral i/o register is read (excluding t he bit manipulation instructions) or the internal ram is accessed after the prcmd register is wri tten and before the special register is written, the prerr flag is not set and setting data can be written to the special registers other than the wdtm register (i.e., the pcc and psc registers). (b) clear condition (prerr = 0) (i) when 0 is written to the prerr flag of the sys register (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcmd register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to th e prcmd register, which is not a sp ecial register, immediately after a write access to the prcmd register , the prerr bit is set to 1. chapter 3 cpu function user?s manual u15905ej2v1ud 87 3.4.9 notes be sure to set the following register first when using the v850es/sa2 and v850es/sa3: ? system wait control register (vswc) after setting the vswc register, set the other registers as necessary. when using the external bus, initialize each register in the following order after setting the above register. <1> set each pin to the control mode by using the port-related registers. (1) system wait control register (vswc) the system wait control register (vswc) controls wait of bus access to t he internal peripheral i/o registers. three clocks are required to access an in ternal peripheral i/o register (wit hout a wait cycle) . the v850es/sa2 and v850es/sa3 require wait cycles according to the operating frequency. set the following value to the vswc register in accordance with the frequency used. the vswc register can be read or written in 8-bit units (address: fffff06eh, default value: 77h). operating frequency (f clk ) set value of vswc 2 mhz f clk < 16.6 mhz 00h 16.6 mhz f clk 20 mhz 01h (2) access to special internal peripheral i/o registers when accessing the following registers, if the cpu acce sses the register at the same time the register changes due to hardware processing, a wait operation is generated for the register access. in this case, it may take longer to access the internal peripheral i/o registers compared with ordinary access. peripheral function target register name dma dtfr0 to dtfr3 timer n (n = 0, 1) tmn, ccn0, ccn1, tmcn0 watchdog timer wdtm uartn (n = 0, 1) asisn i 2 c bus iics caution when the cpu operates on the subclo ck and main oscillation is stopped, access to a register for which a wait is generated is prohi bited. if a wait is generated, only reset can release the wait. user?s manual u15905ej2v1ud 88 chapter 4 port functions 4.1 features 4.1.1 v850es/sa2 input ports: 14 pins i/o ports: 68 pins i/o pins function alternately as other peripheral functions can be set to input or output mode in 1-bit units. 4.1.2 v850es/sa3 input ports: 18 pins i/o ports: 84 pins i/o pins function alternately as other peripheral functions can be set to input or output mode in 1-bit units. chapter 4 port functions user?s manual u15905ej2v1ud 89 4.2 basic configuration of port 4.2.1 v850es/sa2 the v850es/sa2 has a total of 82 input/output port pins (of wh ich 14 are input-only port pins): ports 0, 3, 4, 7 to 9, cm, cs, ct, dh, and dl. the port configuration is shown below. figure 4-1. port configuration (v850es/sa2) p00 p05 port 0 p90 p915 port 9 pcm0 pcm3 port cm pcs0 pcs3 port cs pct0 pct1 pct4 pct7 port ct pdh0 pdh5 port dh pdl0 pdl15 port dl p30 p32 port 3 p40 p46 port 4 p70 p711 port 7 p80 p81 port 8 chapter 4 port functions user?s manual u15905ej2v1ud 90 4.2.2 v850es/sa3 the v850es/sa3 has a total of 102 input/output port pins (of wh ich 18 are input-only port pins): ports 0, 2 to 4, 7 to 9, cd, cm, cs, ct, dh, and dl. the port configuration is shown below. figure 4-2. port configuration (v850es/sa3) p00 p05 port 0 p90 p915 port 9 pcd1 pcd3 port cd pcm0 pcm5 port cm pcs0 pcs7 port cs pct0 pct7 port ct pdh0 pdh7 port dh pdl0 pdl15 port dl p30 p32 port 3 p20 p22 port 2 p40 p46 port 4 p70 p715 port 7 p80 p81 port 8 chapter 4 port functions user?s manual u15905ej2v1ud 91 4.3 port configuration table 4-1. port configuration (v850es/sa2) item configuration control registers port mode registers (pmn: n = 0, 3, 4, 9, cd, cm, cs, ct, dh, dl) port mode control registers (pmcn: n = 0, 3, 4, 9, cm, cs, ct, dh, dl) port function control registers (pfcn: n = 3, 4, 9) port function registers (pfn: n= 3, 4, 9) pull-up resistor option registers (pun: n = 0, 3, 4, 9) external interrupt rising edge specification registers (intrn: n = 0, 9) external interrupt falling edge specification registers (intfn: n = 0, 9) ports i/o: 68 pins, input: 14 pins pull-up resistor software-controlled: 32 resistors table 4-2. port configuration (v850es/sa3) item configuration control registers port mode registers (pmn: n = 0, 2 to 4, 9, cd, cm ,cs, ct, dh, dl) port mode control registers (pmcn: n = 0, 2 to 4, 9, cm, cs, ct, dh, dl) port function control registers (pfcn: n = 3, 4, 9) port function registers (pfn: n = 2, 3, 4, 9) pull-up resistor option registers (pun: n = 0, 2, 3, 4, 9) external interrupt rising edge specification registers (intrn: n = 0, 9) external interrupt falling edge specification registers (intfn: n = 0, 9) ports i/o: 84 pins, input: 18 pins pull-up resistor software-controlled: 35 resistors chapter 4 port functions user?s manual u15905ej2v1ud 92 4.3.1 port 0 port 0 can be set to the input or output mode in 1-bit units. the number of i/o port bits of each product is the same. commercial name number of i/o port bits v850es/sa2 6-bit i/o port v850es/sa3 6-bit i/o port (1) function of port 0 input/output data can be specified in 1-bi t units by using port register 0 (p0). can be set to the input or output mode in 1-bi t units by using port mode register 0 (pm0). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register 0 (pmc0). an internal pull-up resistor can be connected in 1-bit uni ts by using pull-up resistor option register 0 (pu0). the valid edge of the external interrupt (alternate function) can be set in 1-bit units by using external interrupt falling edge specification register 0 (intf0) and external interrupt rising edge specification register 0 (intr0). port 0 has an alternate function as the following pins table 4-3. alternate-function pins of port 0 pin name alternate-function pin i/o pull note remark p00 nmi p01 intp0/ti2 p02 intp1/ti3 p03 intp2/ti4 p04 intp3/ti5 port 0 p05 intp4 i/o provided ? note software pull-up function chapter 4 port functions user?s manual u15905ej2v1ud 93 (2) registers (a) port register 0 (p0) port register 0 (p0) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0. outputs 1. p0n 0 1 controls output data (in output mode) (n = 0 to 5) p0 0 p05 p04 p03 p02 p01 p00 after reset: undefined r/w address: fffff400h remarks 1. in input mode: when port 0 (p0) is read, the pin level at that time is read. when written, the data written to p0 is written. the input pin is not affected. in output mode: when port 0 (p0) is read, the val ue of p0 is read. when a value is written to p0, it is immediately output. 2. after reset, an undefined value (pin input level) is read from p0 in the input mode. when p0 is read in the output mode, 00h (value of the output latch) is read. (b) port mode register 0 (pm0) this is an 8-bit register that sp ecifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. 1 output mode input mode pm0n 0 1 controls input/output mode (n = 0 to 5) pm0 1 pm05 pm04 pm03 pm02 pm01 pm00 after reset: ffh r/w address: fffff420h chapter 4 port functions user?s manual u15905ej2v1ud 94 (c) port mode control register 0 (pmc0) this is an 8-bit register that spec ifies the port mode or control mode. this register can be read or written in 8-bit or 1-bit units. 0 pmc0 0 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 i/o port intp4 input pmc05 0 1 specifies operation mode of p05 pin i/o port intp3/ti5 input pmc04 0 1 specifies operation mode of p04 pin i/o port intp2/ti4 input pmc03 0 1 specifies operation mode of p03 pin i/o port intp1/ti3 input pmc02 0 1 specifies operation mode of p02 pin i/o port intp0/ti2 input pmc01 0 1 specifies operation mode of p01 pin i/o port nmi input pmc00 0 1 specifies operation mode of p00 pin after reset: 00h r/w address: fffff440h caution a register for select s external interrupts (intp0 to intp3) and timer inputs (ti2 to ti5) is not provided. when using port 0 to input an external interrupt , specify the valid edge of the interrupt request by using the intr0/intf0 register. when using the port for timer input, specify the valid edge of tin by using the tcln register. ? intr0: external interrupt rising edge sp ecification register 0 (r efer to 4.3.1 (2) (f).) ? intf0: external interrupt falling edge speci fication register 0 (refer to 4.3.1 (2) (e).) ? tcln: timer n clock select register (refer to chapter 8 8-bi t tiemr/event counters 2 to 5) chapter 4 port functions user?s manual u15905ej2v1ud 95 (d) pull-up resistor option register 0 (pu0) this is an 8-bit register that specifies connection of an internal pull-up resistor. this register can be read or written in 8-bit or 1-bit units. 0 not connected connected pu0n 0 1 controls connection of internal pull-up resistor (n = 0 to 5) pu0 0 pu05 pu04 pu03 pu02 pu01 pu00 after reset: 00h r/w address: fffffc40h (e) external interrupt falling edge specification register 0 (intf0) this 8-bit register specifies detection of t he falling edge of the external interrupt pins. it can be read or written in 8-bit or 1-bit units. caution set the port mode after cl earing the intf0n and intr0n bits to 0 when switching from the external interrupt function (alt ernate function) to the port function because an edge may be detected. 0 intf0 0 intf05 intf04 intf03 intf02 intr01 intr00 after reset: 00h r/w address: fffffc00h intp4 intp3 intp2 intp1 intp0 nmi remark for how to specify a valid edge, refer to table 4-4 . chapter 4 port functions user?s manual u15905ej2v1ud 96 (f) external interrupt rising edge specification register 0 (intr0) this 8-bit register specifies detection of t he rising edge of the external interrupt pins. it can be read or written in 8-bit or 1-bit units. caution set the port mode after cl earing the intf0n and intr0n bits to 0 when switching from the external interrupt function (alt ernate function) to the port function because an edge may be detected. 0 intr0 0 intr05 intr04 intr03 intr02 intr01 intr00 after reset: 00h r/w address: fffffc20h intp4 intp3 intp2 intp1 intp0 nmi remark for how to specify a valid edge, refer to table 4-4 . table 4-4. specifying valid edge intf0n intr0n specifies valid edge (n = 0 to 5) 0 0 detects no edge. 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 0: control of nmi pin n = 1 to 5: control of intp0 to intp4 pins chapter 4 port functions user?s manual u15905ej2v1ud 97 (3) block diagram figure 4-3. block diagram of p00 and p05 internal bus wr pmc rd address nmi, intp4 input wr port p00/nmi, p05/intp4 pmc0n wr intf intf0n selector selector wr pu pu0n wr pm pm0n output latch (p0n) noise elimination, edge detection wr intr intr0n pmc0 intf0 pu0 pm0 p0 intr0 ev dd p-ch caution these pins do not have hysteresis characteristics in the port mode. they have hysteresis characteristics only when an input-pin alternat e function is used. remarks 1. p0: port register 0 pm0: port mode register 0 pmc0: port mode control register 0 pu0: pull-up resistor option register 0 intr0: external interrupt rising edge specification register 0 intf0: external interrupt falling edge specification register 0 2. n = 0, 5 chapter 4 port functions user?s manual u15905ej2v1ud 98 figure 4-4. block diagram of p01 to p04 internal bus wr pmc rd address intp0 to intp3 input ti2 to ti5 input wr port p01/intp0/ti2, p02/intp1/ti3, p03/intp2/ti4, p04/intp3/ti5 pmc0n wr intf intf0n selector selector wr pu pu0n wr pm pm0n output latch (p0n) noise elimination edge detection wr intr intr0n pmc0 intf0 pu0 pm0 p0 intr0 ev dd p-ch caution these pins do not have hysteresis characteristics in the port mode. they have hysteresis characteristics only when an input-pin alternat e function is used. remarks 1. p0: port register 0 pm0: port mode register 0 pmc0: port mode control register 0 pu0: pull-up resistor option register 0 intr0: external interrupt rising edge specification register 0 intf0: external interrupt falling edge specification register 0 2. n = 1 to 4 chapter 4 port functions user?s manual u15905ej2v1ud 99 4.3.2 port 2 port 2 can be set to the input or output mode in 1-bit units. the number of i/o port bits di ffers depending on the product. commercial name number of i/o port bits v850es/sa2 ? v850es/sa3 3-bit i/o port (1) functions of port 2 (v850es/sa3) input/output data can be specified in 1-bi t units by using port register 2 (p2). can be set to the input or output mode in 1-bi t units by using port mode register 2 (pm2). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register 2 (pmc2). n-ch open-drain output can be set in 1-bit un its by using port function register 2 (pf2). an internal pull-up resistor can be connected in 1-bit uni ts by using pull-up resistor option register 2 (pu2). port 2 has an alternate function as the following pins. table 4-5. alternate-function pins of port 2 (v850es/sa3) pin name alternate-function pin i/o pull note remark p20 si4 ? p21 so4 port 2 p22 sck4 i/o provided n-ch open-drain output selectable note software pull-up function chapter 4 port functions user?s manual u15905ej2v1ud 100 (2) registers (a) port register 2 (p2) port register 2 (p2) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0. outputs 1. p2n 0 1 controls output data (in output mode) (n = 0 to 2) p2 0 0 0 0 p22 p21 p20 after reset: undefined r/w address: fffff404h remarks 1. in input mode: when port 2 (p2) is read, the pin level at that time is read. when written, the data written to p2 is written. the input pin is not affected. in output mode: when port 2 (p2) is read, the val ue of p2 is read. when a value is written to p2, it is immediately output. 2. after reset, an undefined value (pin input level) is read from p2 in the input mode. when p2 is read in the output mode, 00h (value of the output latch) is read. (b) port mode register 2 (pm2) this is an 8-bit register that sp ecifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. 1 output mode input mode pm2n 0 1 controls input/output mode (n = 0 to 2) pm2 1 1 1 1 pm22 pm21 pm20 after reset: ffh r/w address: fffff424h chapter 4 port functions user?s manual u15905ej2v1ud 101 (c) port mode control register 2 (pmc2) this is an 8-bit register that spec ifies the port mode or control mode. this register can be read or written in 8-bit or 1-bit units. 0 pmc2 0 0 0 0 pmc22 pmc21 pmc20 i/o port sck4 i/o pmc22 0 1 specifies operation mode of p22 pin i/o port so4 output pmc21 0 1 specifies operation mode of p21 pin i/o port si4 input pmc20 0 1 specifies operation mode of p20 pin after reset: 00h r/w address: fffff444h (d) port function register 2 (pf2) this 8-bit register specifies norma l output or n-ch open-drain output. it can be read or written in 8-bit or 1-bit units. 0 normal output n-ch open-drain output pf2n 0 1 controls normal output or n-ch open-drain output (n = 1, 2) pf2 0 0 0 0 pf22 pf21 0 after reset: 00h r/w address: fffffc64h cautions 1. the n-ch open-drain output voltag e is the normal voltage, not the medium voltage. 2. pf2n = 1 is enabled only in the followin g cases. otherwise, the setting is prohibited. n = 1: so4 n = 2: sck4 chapter 4 port functions user?s manual u15905ej2v1ud 102 (e) pull-up resistor option register 2 (pu2) this is an 8-bit register that specifies connection of an internal pull-up resistor. this register can be read or written in 8-bit or 1-bit units. 0 not connected connected pu2n 0 1 controls connection of internal pull-up resistor (n = 0 to 2) pu2 0 0 0 0 pu22 pu21 pu20 after reset: 00h r/w address: fffffc44h chapter 4 port functions user?s manual u15905ej2v1ud 103 (3) block diagram figure 4-5. block diagram of p20 internal bus wr pmc rd address si4 input wr port p20/si4 pmc20 output latch (p20) selector selector wr pu pu20 wr pm pm20 pmc2 p2 pu2 pm2 ev dd p-ch caution this pin does not have hysteresis characteristics in the port mode. it has hysteresis character istics only when an input-pin alternate function is used. remark p2: port register 2 pm2: port mode register 2 pmc2: port mode control register 2 pu2: pull-up resistor option register 2 chapter 4 port functions user?s manual u15905ej2v1ud 104 figure 4-6. block diagram of p21 internal bus wr pmc rd address so4 output wr port p21/so4 pmc21 selector selector selector wr pu pu21 wr pm pm21 output latch (p21) wr pf pf21 pmc2 pu2 pm2 p2 pf2 ev dd p-ch ev dd ev ss p-ch n-ch remark p2: port register 2 pm2: port mode register 2 pmc2: port mode control register 2 pu2: pull-up resistor option register 2 chapter 4 port functions user?s manual u15905ej2v1ud 105 figure 4-7. block diagram of p22 internal bus wr pmc rd address sck4 output sck4 input sck4 output enable signal wr port p22/sck4 pmc22 selector selector selector wr pu pu22 wr pm pm22 output latch (p22) wr pf pf22 pmc2 pu2 pm2 p2 pf2 ev dd p-ch ev dd ev ss p-ch n-ch caution this pin does not have hysteresis characteristics in the port mode. it has hysteresis character istics only when an input-pin alternate function is used. remark p2: port register 2 pm2: port mode register 2 pmc2: port mode control register 2 pf2: port function register 2 pu2: pull-up resistor option register 2 chapter 4 port functions user?s manual u15905ej2v1ud 106 4.3.3 port 3 port 3 can be set to the input or output mode in 1-bit units. the number of i/o port bits of each product is the same. commercial name number of i/o port bits v850es/sa2 3-bit i/o port v850es/sa3 3-bit i/o port (1) functions of port 3 input/output data can be specified in 1-bi t units by using port register 3 (p3). can be set to the input or output mode in 1-bi t units by using port mode register 3 (pm3). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register 3 (pmc3). control mode 1 or control mode 2 can be specified in 1-bit units by using port function control register 3 (pfc3). n-ch open-drain output can be set in 1-bit un its by using port function register 3 (pf3). an internal pull-up resistor can be connected in 1-bit uni ts by using pull-up resistor option register 3 (pu3). port 3 has an alternate function as the following pins. table 4-6. alternate-function pins of port 3 pin name alternate-function pin i/o pull note remark p30 si1/rxd0 ? p31 so1/txd0 port 3 p32 sck0 i/o provided n-ch open-drain output selectable note software pull-up function chapter 4 port functions user?s manual u15905ej2v1ud 107 (2) registers (a) port register 3 (p3) port register 3 (p3) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0. outputs 1. p3n 0 1 controls output data (in output mode) (n = 0 to 2) p3 0 0 0 0 p32 p31 p30 after reset: undefined r/w address: fffff406h remarks 1. in input mode: when port 3 (p3) is read, the pin level at that time is read. when written, the data written to p3 is written. the input pin is not affected. in output mode: when port 3 (p3) is read, the val ue of p3 is read. when a value is written to p3, it is immediately output. 2. after reset, an undefined value (pin input level) is read from p3 in the input mode. when p3 is read in the output mode, 00h (value of the output latch) is read. (b) port mode register 3 (pm3) this is an 8-bit register that sp ecifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. 1 output mode input mode pm3n 0 1 controls input/output mode (n = 0 to 2) pm3 1 1 1 1 pm32 pm31 pm30 after reset: ffh r/w address: fffff426h chapter 4 port functions user?s manual u15905ej2v1ud 108 (c) port mode control register 3 (pmc3) this is an 8-bit register that spec ifies the port mode or control mode. this register can be read or written in 8-bit or 1-bit units. 0 pmc3 0 0 0 0 pmc32 pmc31 pmc30 i/o port sck1 i/o pmc32 0 1 specifies operation mode of p32 pin i/o port so1/txd0 output pmc31 0 1 specifies operation mode of p31 pin i/o port si1/rxd0 input pmc30 0 1 specifies operation mode of p30 pin after reset: 00h r/w address: fffff446h (d) port function control register 3 (pfc3) this 8-bit register specifies control mode 1 or control mode 2. it can be read or written in 8-bit or 1-bit units. pfc3 after reset: 00h r/w address: fffff466h 0 0 0 0 0 0 pfc31 pfc30 so1 output txd0 output pfc31 0 1 specifies operation mode of p31 pin in control mode si1 input rxd0 input pfc30 0 1 specifies operation mode of p30 pin in control mode chapter 4 port functions user?s manual u15905ej2v1ud 109 (e) port function register 3 (pf3) this 8-bit register specifies norma l output or n-ch open-drain output. it can be read or written in 8-bit or 1-bit units. 0 normal output n-ch open-drain output pf3n 0 1 controls normal output or n-ch open-drain output (n = 1, 2) pf3 0 0 0 0 pf32 pf31 0 after reset: 00h r/w address: fffffc66h cautions 1. the n-ch open-drain output voltag e is the normal voltage, not the medium voltage. 2. pf3n = 1 is enabled only in the followin g cases. otherwise, the setting is prohibited. n = 1: so1 n = 2: sck1 (f) pull-up resistor opt ion register 3 (pu3) this is an 8-bit register that specifies connection of an internal pull-up resistor. this register can be read or written in 8-bit or 1-bit units. 0 not connected. connected. pu3n 0 1 controls connection of internal pull-up resistor (n = 0 to 2) pu3 0 0 0 0 pu32 pu31 pu30 after reset: 00h r/w address: fffffc46h chapter 4 port functions user?s manual u15905ej2v1ud 110 (3) block diagram figure 4-8. block diagram of p30 internal bus wr pmc rd address si1 input rxd0 input wr port p30/si1/rxd0 pmc30 output latch (p30) selector selector selector wr pu pu30 wr pm pm30 wr pfc pfc30 pmc3 p3 pu3 pm3 pfc3 ev dd p-ch caution this pin does not have hysteresis characteristics in the port mode. it has hysteresis character istics only when an input-pin alternate function is used. remark p3: port register 3 pm3: port mode register 3 pmc3: port mode control register 3 pfc3: port function control register 3 pu3: pull-up resistor option register 3 chapter 4 port functions user?s manual u15905ej2v1ud 111 figure 4-9. block diagram of p31 internal bus wr pmc rd address so1 output txd0 output wr port p31/so1/ txd0 pmc31 wr pmc pfc31 selector selector selector selector wr pu pu31 wr pm pm31 output latch (p31) wr pf pf31 pmc3 pfc3 pu3 pm3 p3 pf3 ev dd p-ch ev dd ev ss p-ch n-ch remark p3: port register 3 pm3: port mode register 3 pmc3: port mode control register 3 pfc3: port function control register 3 pf3: port function register 3 pu3: pull-up resistor option register 3 chapter 4 port functions user?s manual u15905ej2v1ud 112 figure 4-10. block diagram of p32 internal bus wr pmc rd address sck1 output sck1 input sck1 output enable signal wr port p32/sck1 pmc32 selector selector selector wr pu pu32 wr pm pm32 output latch (p32) wr pf pf32 pmc3 pu3 pm3 p3 pf3 ev dd p-ch ev dd ev ss p-ch n-ch caution this pin does not have hysteresis characteristics in the port mode. it has hysteresis character istics only when an input-pin alternate function is used. remark p3: port register 3 pm3: port mode register 3 pmc3: port mode control register 3 pfc3: port function control register 3 pu3: pull-up resistor option register 3 chapter 4 port functions user?s manual u15905ej2v1ud 113 4.3.4 port 4 port 4 can be set to the input or output mode in 1-bit units. the number of i/o port bits each product is the same. commercial name number of i/o port bits v850es/sa2 7-bit i/o port v850es/sa3 7-bit i/o port (1) functions of port 4 input/output data can be specified in 1-bi t units by using port register 4 (p4). can be set to the input or output mode in 1-bi t units by using port mode register 4 (pm4). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register 4 (pmc4). control mode 1 or control mode 2 can be specified in 1-bit units by using port function control register 4 (pfc4). n-ch open-drain output can be set to 1-bit uni ts by using port function register 4 (pf4). the internal pull-up resistor can be connected in 1-bit uni ts by using pull-up resistor option register 4 (pu4). port 4 has an alternate function as the following pins. table 4-7. alternate-function pins of port 4 pin name alternate-function pin i/o pull note 1 remark p40 si0 p41 so0/sda note 2 p42 sck0/scl note 2 p43 intp00/ti0/tclr0 p44 intp01/to0 p45 intp01/ti1/tclr1 port 4 p46 intp11/to1 i/o provided ? notes 1. software pull-up function 2. pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only chapter 4 port functions user?s manual u15905ej2v1ud 114 (2) registers (a) port register 4 (p4) port register 4 (p4) is an 8-bit regist er that controls reading the pin leve l and writing the output level. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0. outputs 1. p4n 0 1 controls output data (in output mode) (n = 0 to 6) p4 p46 p45 p44 p43 p42 p41 p40 after reset: undefined r/w address: fffff408h remarks 1. in input mode: when port 4 (p4) is read, the pin level at that time is read. when written, the data written to p4 is written. the input pin is not affected. in output mode: when port 4 (p4) is read, the val ue of p4 is read. when a value is written to p4, it is immediately output. 2. after reset, an undefined value (pin input level) is read from p4 in the input mode. when p4 is read in the output mode, 00h (value of the output latch) is read. (b) port mode register 4 (pm4) this is an 8-bit register that sp ecifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. 1 output mode input mode pm4n 0 1 controls input/output mode (n = 0 to 6) pm4 pm46 pm45 pm44 pm43 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h chapter 4 port functions user?s manual u15905ej2v1ud 115 (c) port mode control register 4 (pmc4) this is an 8-bit register that spec ifies the port mode or control mode. this register can be read or written in 8-bit or 1-bit units. 0 pmc4 pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 i/o port intp11/to1 i/o pmc46 0 1 specifies operation mode of p46 pin i/o port intp10/ti1/tclr1 input pmc45 0 1 specifies operation mode of p45 pin i/o port intp01/to0 i/o pmc44 0 1 specifies operation mode of p44 pin i/o port intp00/ti0/tclr0 input pmc43 0 1 specifies operation mode of p43 pin after reset: 00h r/w address: fffff448h i/o port sck0/scl note i/o pmc42 0 1 specifies operation mode of p42 pin i/o port so0 output /sda note i/o pmc41 0 1 specifies operation mode of p41 pin i/o port si0 input pmc40 0 1 specifies operation mode of p40 pin note pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only cautions 1. to use intp0n, perform the following setting: ? cmsn0 bit of tmcn1 register = 0 ? etin bit of tmcn1 register = 1 ? setting of valid edge by sesn register 2. to use tin, perform the following setting: ? cmsn0 bit of tmcn1 register = 1 ? etin bit of tmcn1 register = 1 ? setting of valid edge by sesn register 3. to use tclrn, perform the following setting: ? eclrn bit of tmcn1 register = 1 ? setting of valid edge by sesn register remark n = 0 or 1 chapter 4 port functions user?s manual u15905ej2v1ud 116 (d) port function control register 4 (pfc4) this 8-bit register specifies control mode 1 or control mode 2. it can be read or written in 8-bit or 1-bit units. pfc4 after reset: 00h r/w address: fffff468h 0 pfc46 0 pfc44 0 pfc42 pfc41 0 intp11 input to1 output note 1 pfc46 0 1 specifies operation mode of p46 pin in control mode intp01 input to0 output note 1 pfc44 0 1 specifies operation mode of p44 pin in control mode sck0 i/o scl i/o note 2 pfc42 0 1 specifies operation mode of p42 pin in control mode so0 output sda i/o note 2 pfc41 0 1 specifies operation mode of p41 pin in control mode notes 1. setting of pcf44 and pcf46 = 1 is enabled onl y when ton output is enabled (enton of tmcn1 register = 1: n = 0 or 1). otherwise, this setting is prohibited. 2. pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only caution the pfc4n bit is valid only when the pmc4n bit = 1 (n = 1, 2, 4, or 6). chapter 4 port functions user?s manual u15905ej2v1ud 117 (e) port function register 4 (pf4) this 8-bit register specifies norma l output or n-ch open-drain output. it can be read or written in 8-bit or 1-bit units. 0 normal output n-ch open-drain output pf4n 0 1 controls normal output or n-ch open-drain output (n = 1, 2) pf4 0 0 0 0 pf42 pf41 0 after reset: 00h r/w address: fffffc68h cautions 1. the n-ch open-drain output voltag e is the normal voltage, not the medium voltage. 2. pf4n = 1 is enabled only in the followin g cases. otherwise, the setting is prohibited. n = 1: so0, sda n = 2: sck0, scl 3. be sure to set n-ch open-drain output when using i 2 c (the sda and scl pins). 4. follow the procedure below to set n-ch open drain. <1> set the p4n bit to 1. <2> set the pf4n bit to 1. <3> set the csie0 bit of the csim0 register or the iice bit of the iicc register to 1. <4> set the pfc4n bit. <5> set the pmc4n bit to 1. (f) pull-up resistor opt ion register 4 (pu4) this is an 8-bit register that specifies connection of an internal pull-up resistor. this register can be read or written in 8-bit or 1-bit units. 0 not connected. connected. pu4n 0 1 controls connection of internal pull-up resistor (n = 0 to 6) pu4 pu46 pu45 pu44 pu43 pu42 pu41 pu40 after reset: 00h r/w address: fffffc48h chapter 4 port functions user?s manual u15905ej2v1ud 118 (3) block diagram figure 4-11. block diagram of p40 internal bus wr pmc rd address si0 input wr port p40/si0 pmc40 output latch (p40) selector selector wr pu pu40 wr pm pm40 pmc4 p4 pu4 pm4 ev dd p-ch caution this pin does not have hysteresis characteristics in the port mode. it has hysteresis character istics only when an input-pin alternate function is used. remark p4: port register 4 pm4: port mode register 4 pmc4: port mode control register 4 pu4: pull-up resistor option register 4 chapter 4 port functions user?s manual u15905ej2v1ud 119 figure 4-12. block diagram of p41 internal bus wr pmc rd address so0 output sda output sda input wr port p41/so0/ sda pmc41 wr pfc pfc41 selector selector selector selector wr pu pu41 wr pm pm41 output latch (p41) wr pf pf41 pmc4 pfc4 pu4 pm4 p4 pf4 ev dd p-ch ev dd ev ss p-ch n-ch caution this pin does not have hysteresis characteristics in the port mode. it has hysteresis character istics only when an input-pin alternate function is used. remark p4: port register 4 pm4: port mode register 4 pmc4: port mode control register 4 pfc4: port function control register 4 pf4: port function register 4 pu4: pull-up resistor option register 4 chapter 4 port functions user?s manual u15905ej2v1ud 120 figure 4-13. block diagram of p42 internal bus wr pmc rd address sck0 output sck0 input scl input sck0 output enable signal wr port p42/sck0/ scl pmc42 wr pfc pfc42 selector selector selector selector wr pu pu42 wr pm pm42 output latch (p42) wr pf pf42 pmc4 pfc4 pu4 pm4 p4 pf4 ev dd p-ch ev dd ev ss p-ch n-ch scl output caution this pin does not have hysteresis characteristics in the port mode. it has hysteresis character istics only when an input-pin alternate function is used. remark p4: port register 4 pm4: port mode register 4 pmc4: port mode control register 4 pfc4: port function control register 4 pf4: port function register 4 pu4: pull-up resistor option register 4 chapter 4 port functions user?s manual u15905ej2v1ud 121 figure 4-14. block diagram of p43 and p45 internal bus wr pmc rd address intp00/ti0/tclr0, intp10/ti1/tclr1 input wr port p43/intp00/ti0/tclr0, p45/intp10/ti1/tclr1 pmc4n output latch (p4n) selector selector wr pu pu4n wr pm pm4n pmc4 p4 pu4 pm4 ev dd p-ch noise elimination caution these pins do not have hysteresis characteristics in the port mode. they have hysteresis characteristics only when an input-pin alternat e function is used. remarks 1. p4: port register 4 pm4: port mode register 4 pmc4: port mode control register 4 pu4: pull-up resistor option register 4 2. n = 3 or 5 chapter 4 port functions user?s manual u15905ej2v1ud 122 figure 4-15. block diagram of p44 and p46 internal bus wr pmc rd address to0, to1 output wr port p44/intp01/to0, p46/intp11/to1 pmc4n selector selector selector wr pu pu4n wr pm pm4n output latch (p4n) wr pfc pfc4n pmc4 pu4 pm4 p4 pfc4 ev dd p-ch intp01, intp11 input noise elimination caution these pins do not have hysteresis characteristics in the port mode. they have hysteresis characteristics only when an input-pin alternat e function is used. remarks 1. p4: port register 4 pm4: port mode register 4 pmc4: port mode control register 4 pfc4: port function control register 4 pu4: pull-up resistor option register 4 2. n = 4 or 6 chapter 4 port functions user?s manual u15905ej2v1ud 123 4.3.5 port 7 all the pins of port 7 are fixed to the input mode. the number of input port bits differs depending on the product. commercial name number of i/o port bits v850es/sa2 12-bit input port v850es/sa3 16-bit input port (1) function of port 7 input data can be specified in 1-bit un its by using port register 7 (p7). port 7 has an alternate function as the following pins. table 4-8. alternate-function pins of port 7 pin name alternate-function pin i/o pull note 1 remark p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p77 ani5 p76 ani6 p77 ani7 p78 ani8 p79 ani9 p710 ani10 p711 ani11 p712 note 2 ani12 note 2 p713 note 2 ani13 note 2 p714 note 2 ani14 note 2 port 7 p715 note 2 ani15 note 2 input none ? notes 1. software pull-up function 2. v850es/sa3 only chapter 4 port functions user?s manual u15905ej2v1ud 124 (2) register (a) port register 7 (p7) port register 7 is a 16-bit register that is used to read the pin level. this register is read-only, in 16-bit units. if the higher 8 bits of the p7 register are used as p7h, and the lower 8 bits as p7l, however, this register can be read in 8-bit or 1-bit units. inputs low level. inputs high level. p7n 0 1 reads input data (v850es/sa2: n = 0 to 12, v850es/sa3: n = 0 to 15) p7 (p7h note 1 ) (p7l) after reset: undefined r address: p7 fffff40eh, p7l fffff40eh, p7h fffff40fh p77 p76 p75 p74 p73 p72 p71 p70 p715 note 2 p714 note 2 p713 note 2 p712 note 2 p711 p710 p79 p78 8 9 10 11 12 13 14 15 notes 1. when reading or writing bits 8 to 15 of the p7 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p7h register. 2. bits 15 to 12 are valid only in the v850es/sa3. these bits are undefined in the v850es/sa2. caution do not read the p7 re gister during a/d conversion. remarks 1. if port 7 (p7) is read, the pin levels at that time can be read. 2. after reset, an undefined value (pin input level) is read when p7 is read. (3) block diagram figure 4-16. block diagram of p70 to p715 internal bus rd ani0 to ani15 input p70/ani0 to p715/ani15 chapter 4 port functions user?s manual u15905ej2v1ud 125 4.3.6 port 8 port 8 can control input/output in 1-bit units. the number of i/o port bits of each product is the same. commercial name number of i/o port bits v850es/sa2 2-bit i/o port v850es/sa3 2-bit i/o port (1) function of port 8 input data can be specified in 1-bit un its by using port register 8 (p8). port 8 has an alternate function as the following pins. table 4-9. alternate-function pins of port 8 pin name alternate-function pin i/o pull note remark p80 ano0 port 8 p81 ano1 input none ? note software pull-up function (2) register (a) port register 8 (p8) port register 8 (p8) is an 8-bit register that is used to read the pin level. this register is read-only, in 8-bit or 1-bit units. 0 inputs low level. inputs high level. p8n 0 1 reads input data (n = 0 or 1) p8 0 0 0 0 0 p81 p80 after reset: undefined r address: fffff410h remarks 1. if port 8 (p8) is read, the pin levels at that time can be read. 2. after reset, an undefined value (pin input level) is read when p8 is read. chapter 4 port functions user?s manual u15905ej2v1ud 126 (3) block diagram figure 4-17. block diagram of p80 and p81 internal bus rd p80/ano0, p81/ano1 p-ch n-ch ano0, ano1 output chapter 4 port functions user?s manual u15905ej2v1ud 127 4.3.7 port 9 port 9 can be set to the input or output mode in 1-bit units. the number of i/o port bits each product is the same. commercial name number of i/o port bits v850es/sa2 16-bit i/o port v850es/sa3 16-bit i/o port (1) functions of port 9 input/output data can be specified in 1-bi t units by using port register 9 (p9). can be set to the input or output mode in 1-bi t units by using port mode register 9 (pm9). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register 9 (pmc9). n-ch open-drain output can be set in 1-bit un its by using port function register 9 (pf9). control mode 1 or control mode 2 can be specified in 1-bit units by using port function control register 9 (pfc9). the internal pull-up resistor can be connected in 1-bit uni ts by using pull-up resistor option register 9 (pu9). the valid edge of the external interrupt (alternate function) can be set in 1-bit units by using external interrupt falling edge specification register 9 (intf9) and external interrupt rising edge specification register 9 (intr9). port 9 has an alternate function as the following pins. table 4-10. alternate-function pins of port 9 pin name alternate-function pin i/o pull note remark p90 a0 p91 a1 p92 a2/intp5 p93 a3/intp6 p94 a4/to2 p95 a5/to3 p96 a6/to4 p97 a7/to5 p98 a8/rxd1 p99 a9/txd1 p910 a10/si2 p911 a11/so2 p912 a12/sck2 p913 a13/si3 p914 a14/so3 port 9 p915 a15/sck3 i/o none ? note software pull-up function chapter 4 port functions user?s manual u15905ej2v1ud 128 (2) registers (a) port register 9 (p9) port register 9 (p9) is a 16-bit regist er that controls reading a pin level and writing an output level. this register can be read or written in 16-bit units. if the higher 8 bits of the p9 register is used as p9h and the lower 8 bits as p9l, however, p9h and p9l can be manipulated in 8-bit or 1-bit units. p915 outputs 0. outputs 1. p9n 0 1 controls output data (in output mode) (n = 0 to 15) p9 (p9h note ) (p9l) p914 p913 p912 p911 p910 p99 p98 after reset: undefined r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 note when reading or writing bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p9h register. remarks 1. in input mode: when port 9 (p9) is read, the pin level at that time is read. when written, the data written to p9 is written. the input pin is not affected. in output mode: when port 9 (p9) is read, the val ue of p9 is read. when a value is written to p9, it is immediately output. 2. after reset, an undefined value (pin input level) is read from p9 in the input mode. when p9 is read in the output mode, 00h (value of the output latch) is read. chapter 4 port functions user?s manual u15905ej2v1ud 129 (b) port mode register 9 (pm9) this is a 16-bit register that sp ecifies the input or output mode. this register can be read or written only in 16-bit units. if the higher 8 bits of the pm9 register is used as pm 9h and the lower 8 bits as pm9l, however, pm9h and pm9l can be manipulated in 8-bit or 1-bit units. pm97 output mode input mode pm9n 0 1 controls input/output mode (n = 0 to 15) pm96 pm95 pm94 pm93 pm92 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 (pm9h note ) (pm9l) pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 note when reading or writing bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm9h register. chapter 4 port functions user?s manual u15905ej2v1ud 130 (c) port mode control register 9 (pmc9) this is a 16-bit register that spec ifies the port mode or control mode. this register can be read or written only in 16-bit units. if the higher 8 bits of the pmc9 register is used as pmc9h and the lower 8 bits as pmc9l, however, pmc9h and pmc9l can be manipulated in 8-bit or 1-bit units. (1/2) i/o port a15/sck3 i/o pmc915 0 1 specifies operation mode of p915 pin pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc9 (pmc9h note ) (pmc9l) pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 i/o port a14/so3 output pmc914 0 1 specifies operation mode of p914 pin i/o port a11/so2 output pmc911 0 1 specifies operation mode of p911 pin i/o port a10/si2 i/o pmc910 0 1 specifies operation mode of p910 pin i/o port a9/txd1 output pmc99 0 1 specifies operation mode of p99 pin i/o port a8/rxd1 i/o pmc98 0 1 specifies operation mode of p98 pin i/o port a13/si3 i/o pmc913 0 1 specifies operation mode of p913 pin i/o port a12/sck2 i/o pmc912 0 1 specifies operation mode of p912 pin note when reading or writing bits 8 to 15 of the pmc9 regist er in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. chapter 4 port functions user?s manual u15905ej2v1ud 131 (2/2) i/o port a7/to5 output pmc97 0 1 specifies operation mode of p97 pin i/o port a6/to4 output pmc96 0 1 specifies operation mode of p96 pin i/o port a5/to3 output pmc95 0 1 specifies operation mode of p95 pin i/o port a4/to2 output pmc94 0 1 specifies operation mode of p94 pin i/o port a3/intp6 i/o pmc93 0 1 specifies operation mode of p93 pin i/o port a2/intp5 i/o pmc92 0 1 specifies operation mode of p92 pin i/o port a1 output pmc91 0 1 specifies operation mode of p91 pin i/o port a0 output pmc90 0 1 specifies operation mode of p90 pin chapter 4 port functions user?s manual u15905ej2v1ud 132 (d) port function control register 9 (pfc9) this 16-bit register specifies c ontrol mode 1 or control mode 2. it can be read or written only in 16-bit units. if the higher 8 bits of the pfc9 r egister are used as pfc9h and the lo wer 8 bits as pfc9l, however, pfc9h and pfc9l can be manipulated in 8-bit or 1-bit units. caution to perform separate bus address output (a0 to a15), set the pfc9 register to 0000h, and then set the pmc9 register to ffffh in 16-bit units. (1/2) pfc9 (pfc9h note ) (pfc9l) a15 output (with separate bus) sck3 i/o pfc915 0 1 specifies operation mode of p915 pin in control mode a14 output (with separate bus) so3 output pfc914 0 1 specifies operation mode of p914 pin in control mode a13 output (with separate bus) si3 input pfc913 0 1 specifies operation mode of p913 pin in control mode a12 output (with separate bus) sck2 i/o pfc912 0 1 specifies operation mode of p912 pin in control mode after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 0 0 pfc910 pfc910 pfc910 pfc910 pfc910 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 a11 output (with separate bus) so2 output pfc911 0 1 specifies operation mode of p911 pin in control mode a10 output (with separate bus) si2 input pfc910 0 1 specifies operation mode of p910 pin in control mode a9 output (with separate bus) txd1 output pfc99 0 1 specifies operation mode of p99 pin in control mode note when reading or writing bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. chapter 4 port functions user?s manual u15905ej2v1ud 133 (2/2) a8 output (with separate bus) rxd1 input pfc98 0 1 specifies operation mode of p98 pin in control mode a7 output (with separate bus) to5 output pfc97 0 1 specifies operation mode of p97 pin in control mode a6 output (with separate bus) to4 output pfc96 0 1 specifies operation mode of p96 pin in control mode a5 output (with separate bus) to3 output pfc95 0 1 specifies operation mode of p95 pin in control mode a4 output (with separate bus) to2 output pfc94 0 1 specifies operation mode of p94 pin in control mode a3 output (with separate bus) intp6 input pfc93 0 1 specifies operation mode of p93 pin in control mode a2 output (with separate bus) intp5 input pfc92 0 1 specifies operation mode of p92 pin in control mode chapter 4 port functions user?s manual u15905ej2v1ud 134 (e) port function register 9 (pf9) this 16-bit register specifies normal output or n-ch open-drain output. the pf9 register can be read or written only in 16-bit uni ts. if the higher 8 bits of the pf9 register are used as pf9h and the lower 8 bits as pf9l, however, pf9h and pf9l can be manipulated in 8-bit or 1-bit units. pf9 (pf9h note ) after reset: 0000h r/w address: pf9 fffffc72h, pf9h fffffc73h 00 00 000 0 pf915 pf914 0 pf912 pf911 0 0 0 8 9 10 11 12 13 14 15 normal output n-ch open-drain output pf9n 0 1 controls normal output or n-ch open-drain output (n = 11, 12, 14, or 15) note when reading or writing bits 8 to 15 of the pf9 register in 8-bit or 1-bi t units, specify these bits as bits 0 to 7 of the pf9h register. cautions 1. the n-ch open-drain output voltag e is the normal voltage, not the medium voltage. 2. pf9n = 1 is enabled only in the followin g cases. otherwise, the setting is prohibited. n = 1: so2 n = 2: sck2 n = 4: so3 n = 5: sck3 3. follow the procedure below to set n-ch open drain. <1> set the p9n bit to 1. <2> set the pf9n bit to 1. <3> set the csie2 bit of the csim2 register or the csie3 bit of the csim3 register to 1. <4> set the pfc9n bit. <5> set the pmc9n bit to 1. chapter 4 port functions user?s manual u15905ej2v1ud 135 (f) pull-up resistor opt ion register 9 (pu9) this is a 16-bit register that specifies connection of an internal pull-up resistor. this register can be read or written only in 16-bit units. if the higher 8 bits of the pu9 regi ster are used as pu9h and the lower 8 bits as pu9l, however, pu9h and pu9l can be manipulated in 8-bit or 1-bit units. not connected connected pu9n 0 1 controls connection of internal pull-up resistor (n = 0 to 15) pu9 (pu9h note ) (pu9l) after reset: 0000h r/w address: pu9 fffffc52h, pu9l fffffc52h, pu9h fffffc53h pu97 pu96 pu95 pu94 pu93 pu92 pu91 pu90 pu915 pu914 pu913 pu912 pu911 pu910 pu99 pu98 8 9 10 11 12 13 14 15 note when reading or writing bits 8 to 15 of the pu9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pu9h register. (g) external interrupt falling edge specification register 9 (intf9) this 16-bit register specifies detection of t he falling edge of the external interrupt pins. it can be read or written only in 16-bit units. if the hi gher 8 bits of the intf9 register are used as intf9h and the lower 8 bits as intf9l, however, intf9h and intf9l can be manipulated in 8-bit or 1-bit units. caution set the port mode after cl earing the intf9n and intr9n bits to 0 when switching from the external interrupt function (alt ernate function) to the port function because an edge may be detected. intf9 (intf9l) after reset: 0000h r/w address: intf9 fffffc12h, intf9l fffffc12h 0 0 0 0 intf93 intf92 0 0 00 00 00 0 0 8 9 10 11 12 13 14 15 remark for how to specify a valid edge, refer to table 4-11 . chapter 4 port functions user?s manual u15905ej2v1ud 136 (h) external interrupt rising edge specification register 9 (intr9) this 16-bit register specifies detection of t he rising edge of the external interrupt pins. it can be read or written only in 16-bit units. if the hi gher 8 bits of the intr9 register are used as intr9h and the lower 8 bits as intr9l, however, intr9h and intr9l can be manipulated in 8-bit or 1-bit units. caution set the port mode after cl earing the intf9n and intr9n bits to 0 when switching from the external interrupt function (alt ernate function) to the port function because an edge may be detected. intr9 (intr9l) after reset: 0000h r/w address: intr9 fffffc32h, intr9l fffffc32h 0 0 0 0 intr93 intr92 0 0 00 00 00 0 0 8 9 10 11 12 13 14 15 remark for how to specify a valid edge, refer to table 4-11 . table 4-11. specifying valid edge intf9n intr9n specifies valid edge (n = 2 or 3). 0 0 detects no edge. 0 1 rising edge 1 0 falling edge 1 1 both edges caution when intp5 and intp6 are not used, be sure to clear intf9n and intr9n to ?00?. remark n = 2 or 3: control of intp5 or intp6 pin chapter 4 port functions user?s manual u15905ej2v1ud 137 (3) block diagram figure 4-18. block diagram of p90 and p91 internal bus wr pmc rd address a0, a1 output output buffer off signal wr port p90/a0, p91/a1 pmc9n output latch (p9n) selector selector selector selector wr pm pm9n wr pu pu9n pmc9 p9 pm9 pu9 ev dd p-ch remarks 1. p9: port register 9 pm9: port mode register 9 pmc9: port mode control register 9 pu9: pull-up resistor option register 9 output buffer off signal: signal that is active in the idle/stop mode or during bus hold 2. n = 0 or 1 chapter 4 port functions user?s manual u15905ej2v1ud 138 figure 4-19. block diagram of p92 and p93 internal bus wr pmc rd address a2, a3 output wr port p92/a2/intp5, p93/a3/intp6 pmc9n wr pfc pfc9n selector selector output buffer off signal selector selector wr pu pu9n wr pm pm9n output latch (p9n) wr intf intf9n wr intr intr9n pmc9 pfc9 pu9 pm9 p9 intf9 intr9 ev dd p-ch intp5, intp6 input noise elimination, edge detection caution these pins do not have hysteresis characteristics in the port mode. they have hysteresis characteristics only when an input-pin alternat e function is used. remarks 1. p9: port register 9 pm9: port mode register 9 pmc9: port mode control register 9 pfc9: port function control register 9 pu9: pull-up resistor option register 9 intr9: external interrupt rising edge specification register 9 intf9: external interrupt falling edge specification register 9 output buffer off signal: signal that is active in the idle/stop mode or during bus hold 2. n = 2 or 3 chapter 4 port functions user?s manual u15905ej2v1ud 139 figure 4-20. block diagram of p94 to p97 and p99 internal bus wr pmc rd address to2 to to5, txd1 output a4 to a9 output output buffer off signal wr port p94/a4/to2, p95/a5/to3, p96/a6/to4, p97/a7/to5, p99/a9/txd1 pmc9n output latch (p9n) selector selector selector selector selector wr pu pu9n wr pm pm9n wr pfc pfc9n pmc9 p9 pu9 pm9 pfc9 ev dd p-ch remarks 1. p9: port register 9 pm9: port mode register 9 pmc9: port mode control register 9 pf9: port function register 9 pu9: pull-up resistor option register 9 output buffer off signal: signal that is active in the idle/stop mode or during bus hold 2. n = 4 to 7, 9 chapter 4 port functions user?s manual u15905ej2v1ud 140 figure 4-21. block diagram of p98, p910, and p913 internal bus wr pmc rd address a8, a10, a13 output rxd1, si2, si3 input output buffer off signal wr port p98/a8/rxd1, p910/a10/si2, p913/a13/si3 pmc9n output latch (p9n) selector selector selector selector wr pu pu9n wr pm pm9n wr pfc pfc9n pmc9 p9 pu9 pm9 pfc9 ev dd p-ch caution these pins do not have hysteresis characteristics in the port mode. they have hysteresis characteristics only when an input-pin alternat e function is used. remarks 1. p9: port register 9 pm9: port mode register 9 pmc9: port mode control register 9 pf9: port function register 9 pu9: pull-up resistor option register 9 output buffer off signal: signal that is active in the idle/stop mode or during bus hold 2. n = 8, 10, 13 chapter 4 port functions user?s manual u15905ej2v1ud 141 figure 4-22. block diagram of p911 and p914 internal bus wr pmc rd address so2, so3 output a11, a14 output wr port p911/a11/so2, p914/a14/so3 pmc9n wr pfc pfc9n selector selector selector output buffer off signal selector selector wr pu pu9n wr pm pm9n output latch (p9n) wr pf pf9n pmc9 pfc9 pu9 pm9 p9 pf9 ev dd p-ch ev dd ev ss p-ch n-ch remarks 1. p9: port register 9 pm9: port mode register 9 pmc9: port mode control register 9 pfc9: port function control register 9 pf9: port function register 9 pu9: pull-up resistor option register 9 output buffer off signal: signal that is active in the idle/stop mode or during bus hold 2. n = 11, 14 chapter 4 port functions user?s manual u15905ej2v1ud 142 figure 4-23. block diagram of p912 and p915 internal bus wr pmc rd address sck2, sck3 output a12, a15 output sck2, sck3 input wr port p912/a12/sck2, p915/a15/sck3 pmc9n wr pfc pfc9n selector selector selector output enable signal of sck2 and sck3 output buffer off signal selector selector wr pu pu9n wr pm pm9n output latch (p9n) wr pf pf9n pmc9 pfc9 pu9 pm9 p9 pf9 ev dd p-ch ev dd ev ss p-ch n-ch selector caution these pins do not have hysteresis characteristics in the port mode. they have hysteresis characteristics only when an input-pin alternat e function is used. remarks 1. p9: port register 9 pm9: port mode register 9 pmc9: port mode control register 9 pfc9: port function control register 9 pf9: port function register 9 pu9: pull-up resistor option register 9 output buffer off signal: signal that is active in the idle/stop mode or during bus hold 2. n = 12 or 15 chapter 4 port functions user?s manual u15905ej2v1ud 143 4.3.8 port cd port cd can be set to the input or output mode in 1-bit units. the number of i/o port bits di ffers depending on the product. commercial name number of i/o port bits v850es/sa2 ? v850es/sa3 3-bit i/o port (1) functions of port cd (v850es/sa3) input/output data can be specified in 1-bit units by using port register cd (pcd). can be set to the input or output mode in 1-bit units by using port mode register cd (pmcd). port cd has no alternate-function pins. table 4-12. alternate-function pins of port cd (v850es/sa3) pin name alternate-function pin i/o pull note remark pcd1 ? pcd2 ? port cd pcd3 ? i/o none ? note software pull-up function chapter 4 port functions user?s manual u15905ej2v1ud 144 (2) registers (a) port register cd (pcd) port register cd (pcd) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0. outputs 1. pcdn 0 1 controls output data (in output mode) (n = 1 to 3) pcd 0 0 0 pcd3 pcd2 pcd1 0 after reset: undefined r/w address: fffff00eh remarks 1. in input mode: when port cd (pcd) is read, the pin level at that time is read. when written, the data written to pcd is written. the input pin is not affected. in output mode: when port cd (pcd) is read, the value of pcd is read. when a value is written to pcd, it is immediately output. 2. after reset, an undefined value (pin input level) is read from pcd in the input mode. when pcd is read in the output mode, 00h (value of the output latch) is read. (b) port mode register cd (pmcd) this is an 8-bit register that sp ecifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. 1 output mode input mode pmcdn 0 1 controls input/output mode (n = 1 to 3) pmcd 1 1 1 pmcd3 pmcd2 pmcd1 1 after reset: ffh r/w address: fffff02eh chapter 4 port functions user?s manual u15905ej2v1ud 145 (3) block diagram figure 4-24. block diagram of pcd1 to pcd3 internal bus wr pm rd address wr port pcd1 to pcd3 pmcdn output latch (pcdn) pmcd pcd selector selector remarks 1. pcd: port register cd pmcd: port mode register cd 2. n = 1 to 3 chapter 4 port functions user?s manual u15905ej2v1ud 146 4.3.9 port cm port cm can be set to the input or output mode in 1-bit units. the number of i/o port bits di ffers depending on the product. commercial name number of i/o port bits v850es/sa2 4-bit i/o port v850es/sa3 6-bit i/o port (1) functions of port cm input/output data can be specified in 1-bit units by using port register cm (pcm). can be set to the input or output mode in 1-bit units by using port mode register cm (pmcm). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register cm (pmccm). port cm has an alternate function as the following pins. table 4-13. alternate-function pins of port cm pin name alternate-function pin i/o pull note 1 remark pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq pcm4 note 2 ? port cm pcm5 note 2 ? i/o none ? notes 1. software pull-up function 2. v850es/sa3 only chapter 4 port functions user?s manual u15905ej2v1ud 147 (2) registers (a) port register cm (pcm) port register pcm (pcm) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0. outputs 1. pcmn 0 1 controls output data (in output mode) (v850es/sa2: n = 0 to 3, v850es/sa3: n = 0 to 5) pcm 0 pcm5 note pcm4 note pcm3 pcm2 pcm1 pcm0 after reset: undefined r/w address: fffff00ch note bits 5 and 4 are provided in the v850es/sa3 only. be sure to clear these bits to 0 in the v850es/sa2. remarks 1. in input mode: when port cm (pcm) is read, the pi n level at that time is read. when written, the data written to pcm is written. the input pin is not affected. in output mode: when port cm (pcm) is read, t he value of pcm is read. when a value is written to pcm, it is immediately output. 2. after reset, an undefined value (pin input level) is read from pcm in the input mode. when pcm is read in the output mode, 00h (val ue of the output latch) is read. (b) port mode register cm (pmcm) this is an 8-bit register that sp ecifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. 1 output mode input mode pmcmn 0 1 controls input/output mode (v850es/sa2: n = 0 to 3, v850es/sa3: n = 0 to 5) pmcm 1 pmcm5 note pmcm4 note pmcm3 pmcm2 pmcm1 pmcm0 after reset: ffh r/w address: fffff02ch note bits 5 and 4 are provided in the v850es/sa3 only. be sure to set these bits to 1 in the v850es/sa2. chapter 4 port functions user?s manual u15905ej2v1ud 148 (c) port mode control register cm (pmccm) this is an 8-bit register that spec ifies the port mode or control mode. it can be read or written in 8-bit or 1-bit units. 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port hldrq input pmccm3 0 1 specifies operation mode of pcm3 pin i/o port hldak output pmccm2 0 1 specifies operation mode of pcm2 pin i/o port clkout output pmccm1 0 1 specifies operation mode of pcm1 pin i/o port wait input pmccm0 0 1 specifies operation mode of pcm0 pin after reset: 00h r/w address: fffff04ch chapter 4 port functions user?s manual u15905ej2v1ud 149 (3) block diagram figure 4-25. block diagram of pcm0 and pcm3 internal bus wr pmc rd address wait, hldrq input wr port pcm0/wait, pcm3/hldrq pmccmn output latch (pcmn) selector selector wr pm pmcmn pmccm pcm pmcm remarks 1. pcm: port register cm pmcm: port mode register cm pmccm: port mode control register cm 2. n = 0 or 3 chapter 4 port functions user?s manual u15905ej2v1ud 150 figure 4-26. block diagram of pcm1 and pcm2 internal bus wr pmc rd address clkout, hldak output wr port pcm1/clkout, pcm2/hldak pmccmn output latch (pcmn) pcm selector selector selector wr pm pmcmn pmccm pmcm remarks 1. pcm: port register cm pmcm: port mode register cm pmccm: port mode control register cm 2. n = 1 or 2 chapter 4 port functions user?s manual u15905ej2v1ud 151 figure 4-27. block diagram of pcm4 and pcm5 internal bus wr pm rd address wr port pcm4, pcm5 pmcmn output latch (pcmn) pmcm pcm selector selector remarks 1. pcm: port register cm pmcm: port mode register cm 2. n = 4 or 5 chapter 4 port functions user?s manual u15905ej2v1ud 152 4.3.10 port cs port cs can be set to the input or output mode in 1-bit units. the number of i/o port bits di ffers depending on the product. commercial name number of i/o port bits v850es/sa2 4-bit i/o port v850es/sa3 8-bit i/o port (1) functions of port cs input/output data can be specified in 1-bit units by using port register cs (pcs). can be set to the input or output mode in 1-bit units by using port mode register cs (pmcs). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register cs (pmccs). port cs has an alternate function as the following pins. table 4-14. alternate-function pins of port cs pin name alternate-function pin i/o pull note 1 remark pcs0 cs0 pcs1 cs1 pcs2 cs2 pcs3 cs3 pcs4 note 2 ? pcs5 note 2 ? pcs6 note 2 ? port cs pcs7 note 2 ? i/o none ? notes 1. software pull-up function 2. v850es/sa3 only chapter 4 port functions user?s manual u15905ej2v1ud 153 (2) registers (a) port register cs (pcs) port register cs (pcs) is an 8-bit register that contro ls reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. pcs7 note outputs 0. outputs 1. pcsn 0 1 controls output data (in output mode) (v850es/sa2: n = 0 to 3, v850es/sa3: n = 0 to 7) pcs pcs6 note pcs5 note pcs4 note pcs3 pcs2 pcs1 pcs0 after reset: undefined r/w address: fffff008h note bits 7 to 4 are provided in the v850es/sa3 only. be sure to clear these bits to 0 in the v850es/sa2. remarks 1. in input mode: when port cs (pcs) is read, the pi n level at that time is read. when written, the data written to pcs is written. the input pin is not affected. in output mode: when port cs (pcs) is read, the value of pcs is read. when a value is written to pcs, it is immediately output. 2. after reset, an undefined value (pin input level) is read from pcs in the input mode. when pcs is read in the output mode, 00h (value of the output latch) is read. (b) port mode register cs (pmcs) this is an 8-bit register that sp ecifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. pmcs7 note output mode input mode pmcsn 0 1 controls input/output mode (v850es/sa2: n = 0 to 3, v850es/sa3: n = 0 to 7) pmcs pmcs6 note pmcs5 note pmcs4 note pmcs3 pmcs2 pmcs1 pmcs0 after reset: ffh r/w address: fffff028h note bits 7 to 4 are provided in the v850es/sa3 only. be sure to set these bits to 1 in the v850es/sa2. chapter 4 port functions user?s manual u15905ej2v1ud 154 (c) port mode control register cs (pmccs) this is an 8-bit register that spec ifies the port mode or control mode. it can be read or written in 8-bit or 1-bit units. 0 i/o port csn output pmccsn 0 1 specifies operation mode of pcsn pin (n = 0 to 3) pmccs 0 0 0 pmccs3 pmccs2 pmccs1 pmccs0 after reset: 00h r/w address: fffff048h chapter 4 port functions user?s manual u15905ej2v1ud 155 (3) block diagram figure 4-28. block diagram of pcs0 to pcs3 internal bus wr pmc rd address cs0 to cs3 output wr port pcs0/cs0 to pcs3/cs3 pmccsn output latch (pcsn) pcs selector selector selector wr pm pmcsn pmccs pmcs remarks 1. pcs: port register cs pmcs: port mode register cs pmccs: port mode control register cs 2. n = 0 to 3 chapter 4 port functions user?s manual u15905ej2v1ud 156 figure 4-29. block diagram of pcs4 to pcs7 internal bus wr pm rd address wr port pcs4 to pcs7 pmcsn output latch (pcsn) pmcs pcs selector selector remarks 1. pcs: port register cs pmcs: port mode register cs 2. n = 4 to 7 chapter 4 port functions user?s manual u15905ej2v1ud 157 4.3.11 port ct port ct can be set to the input or output mode in 1-bit units. the number of i/o port bits di ffers depending on the product. commercial name number of i/o port bits v850es/sa2 6-bit i/o port v850es/sa3 8-bit i/o port (1) functions of port ct input/output data can be specified in 1-bit units by using port register ct (pct). can be set to the input or output mode in 1-bi t units by using port mode register ct (pmct). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register ct (pmcct). table 4-15. alternate-function pins of port ct pin name alternate-function pin i/o pull note 1 remark pct0 wr0 pct1 wr1 pct2 note 2 ? pct3 note 2 ? pct4 rd pct5 ? pct6 astb port ct pct7 ? i/o none ? notes 1. software pull-up function 2. v850es/sa3 only chapter 4 port functions user?s manual u15905ej2v1ud 158 (2) registers (a) port register ct (pct) port register pct (pct) is an 8-bit register that cont rols reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. pct7 outputs 0. outputs 1. pctn 0 1 controls output data (in output mode) (v850es/sa2: n = 0, 1, 4 to 7, v850es/sa3: n = 0 to 7) pct pct6 pct5 pct4 pct3 note pct2 note pct1 pct0 after reset: undefined r/w address: fffff00ah note bits 3 and 2 are provided in the v850es/sa3 only. be sure to clear these bits to 0 in the v850es/sa2. remarks 1. in input mode: when port ct (pct) is read, the pi n level at that time is read. when written, the data written to pct is written. the input pin is not affected. in output mode: when port ct (pct) is read, t he value of pct is read. when a value is written to pct, it is immediately output. 2. after reset, an undefined value (pin input level) is read from pct in the input mode. when pct is read in the output mode, 00h (value of the output latch) is read. (b) port mode register ct (pmct) this is an 8-bit register that sp ecifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. pmct7 output mode input mode pmctn 0 1 controls input/output mode (v850es/sa2: n = 0, 1, 4 to 7, v850es/sa3: n = 0 to 7) pmct pmct6 pmct5 pmct4 pmct3 note pmct2 note pmct1 pmct0 after reset: ffh r/w address: fffff02ah note bits 3 and 2 are provided in the v850es/sa3 only. be sure to set these bits to 1 in the v850es/sa2. chapter 4 port functions user?s manual u15905ej2v1ud 159 (c) port mode control register ct (pmcct) this is an 8-bit register that spec ifies the port mode or control mode. it can be read or written in 8-bit or 1-bit units. 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port astb output pmcct6 0 1 specifies operation mode of pct6 pin i/o port rd output pmcct4 0 1 specifies operation mode of pct4 pin i/o port wr1 output pmcct1 0 1 specifies operation mode of pct1 pin i/o port wr0 output pmcct0 0 1 specifies operation mode of pct0 pin after reset: 00h r/w address: fffff04ah chapter 4 port functions user?s manual u15905ej2v1ud 160 (3) block diagram figure 4-30. block diagram of pct0, pct1, pct4, and pct6 internal bus wr pmc rd address wr0, wr1, rd, astb output wr port pct0/wr0, pct1/wr1, pct4/rd, pct6/astb pmcctn output latch (pctn) pct selector selector selector wr pm pmctn pmcct pmct remarks 1. pct: port register ct pmct: port mode register ct pmcct: port mode control register ct 2. n = 0, 1, 4, or 6 chapter 4 port functions user?s manual u15905ej2v1ud 161 figure 4-31. block diagram of pct2, pct3, pct5, and pct7 internal bus wr pm rd address wr port pct2, pct3, pct5, pct7 pmctn output latch (pctn) pmct pct selector selector remarks 1. pct: port register ct pmct: port mode register ct 2. n = 2, 3, 5, or 7 chapter 4 port functions user?s manual u15905ej2v1ud 162 4.3.12 port dh port dh can be set to the input or output mode in 1-bit units. the number of i/o port bits di ffers depending on the product. commercial name number of i/o port bits v850es/sa2 6-bit i/o port v850es/sa3 8-bit i/o port (1) functions of port dh input/output data can be specified in 1-bit units by using port register dh (pdh). can be set to the input or output mode in 1-bit units by using port mode register dh (pmdh). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register dh (pmcdh). port dh has an alternate function as the following pins. table 4-16. alternate-function pins of port dh pin name alternate-function pin i/o pull note 1 remark pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 pdh5 a21 pdh6 note 2 a22 note 2 port dh pdh7 note 2 a23 note 2 i/o none ? notes 1. software pull-up function 2. v850es/sa3 only chapter 4 port functions user?s manual u15905ej2v1ud 163 (2) registers (a) port register dh (pdh) port register pdh (pdh) is an 8-bit register that cont rols reading the pin level and writing the output level. this register can be read or written in 8-bit or 1-bit units. outputs 0. outputs 1. pdhn 0 1 controls output data (in output mode) (v850es/sa2: n = 0 to 5, v850es/sa3: n = 0 to 7) pdh after reset: undefined r/w address: fffff006h pdh7 note pdh6 note pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 note bits 7 and 6 are provided in the v850es/sa3 only. be sure to clear these bits to 0 in the v850es/sa2. remarks 1. in input mode: when port dh (pdh) is read, the pi n level at that time is read. when written, the data written to pdh is written. the input pin is not affected. in output mode: when port dh (pdh) is read, the value of pdh is read. when a value is written to pdh, it is immediately output. 2. after reset, an undefined value (pin input level) is read from pdh in the input mode. when pdh is read in the output mode, 00h (value of the output latch) is read. (b) port mode register dh (pmdh) this is an 8-bit register that sp ecifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. pmdh7 note output mode input mode pmdhn 0 1 controls input/output mode (v850es/sa2: n = 0 to 5, v850es/sa3: n = 0 to 7) pmdh6 note pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh note bits 7 and 6 are provided in the v850es/sa3 only. be sure to set these bits to 1 in the v850es/sa2. chapter 4 port functions user?s manual u15905ej2v1ud 164 (c) port mode control register dh (pmcdh) this is an 8-bit register that spec ifies the port mode or control mode. it can be read or written in 8-bit or 1-bit units. i/o port am output (address bus output) (v850es/sa2: m = 16 to 21, v850es/sa3: m = 16 to 23) pmcdhn 0 1 specifies operation mode of pdhn pin (v850es/sa2: n = 0 to 5, v850es/sa3: n = 0 to 7) pmcdh7 note pmcdh6 note pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h pmcdh note bits 7 and 6 are provided in the v850es/sa3 only. be sure to clear these bits to 0 in the v850es/sa2. chapter 4 port functions user?s manual u15905ej2v1ud 165 (3) block diagram figure 4-32. block diagram of pdh0 to pdh7 wr pmc rd wr port pdh0/a16 to pdh7/a23 pmcdhn wr pm pmdhn output latch (pdhn) pmcdh pdh pmdh a16 to a23 output internal bus address selector selector selector selector output buffer off signal remarks 1. pdh: port register dh pmdh: port mode register dh pmcdh: port mode control register dh pudh: pull-up resistor option register dh output buffer off signal: signal that is active in idle/stop mode 2. n = 0 to 7 chapter 4 port functions user?s manual u15905ej2v1ud 166 4.3.13 port dl port dl can be set to the input or output mode in 1-bit units. the number of i/o port bits of each product is the same. commercial name number of i/o port bits v850es/sa2 16-bit i/o port v850es/sa3 16-bit i/o port (1) functions of port dl input/output data can be specified in 1-bit units by using port register dl (pdl). can be set to the input or output mode in 1-bit units by using port mode register dl (pmdl). can be set to the port mode or control mode (alter nate function) in 1-bit units by using port mode control register dl (pmcdl). port dl has an alternate function as the following pins. table 4-17. alternate-function pins of port dl pin name alternate-function pin i/o pull note 1 remark pdl0 ad0 pdl1 ad1 pdl2 ad2 pdl3 ad3 pdl4 ad4 pdl5 ad5/flmd1 note 2 pdl6 ad6 pdl7 ad7 pdl8 ad8 pdldl ad9 pdl10 ad10 pdl11 ad11 pdl12 ad12 pdl13 ad13 pdl14 ad14 port dl pdl15 ad15 i/o none ? notes 1. software pull-up function 2. because these pins are used for setting in the flash programming mode, they do not have to be manipulated by using a port control register. for details, refer to chapter 21 flash memory ( pd70f3201, 70f3201y, 70f3204, and 70f3204y only). chapter 4 port functions user?s manual u15905ej2v1ud 167 (2) registers (a) port register dl (pdl) port register dl (pdl) is a 16-bit register that controls reading the pi n level and writing the output level. this register can be read or written in 8-bit or 1-bit units. if the higher 8 bits of the pdl regi ster are used as pdlh, and the lower 8 bits as pdll, however, pdlh and pdll can be used as an 8-bit i/o port whose input or ou tput can be manipulated in 8-bit or 1-bit units. pdl15 outputs 0. outputs 1. pdln 0 1 controls output data (in output mode) (n = 0 to 15) pdl (pdlh note ) (pdll) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: undefined r/w address: pdl fffff004h, pdll fffff004h, pdlh fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 note when reading or writing bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pdlh register. remarks 1. in input mode: when port dl (pdl) is read, the pi n level at that time is read. when written, the data written to pdl is written. the input pin is not affected. in output mode: when port dl (pdl) is read, the value of pdl is read. when a value is written to pdl, it is immediately output. 2. after reset, an undefined value (pin input level) is read from pdl in the input mode. when pdl is read in the output mode, 0000h (val ue of the output latch) is read. chapter 4 port functions user?s manual u15905ej2v1ud 168 (b) port mode register dl (pmdl) this is a 16-bit register that sp ecifies the input or output mode. this register can be read or written only in 16-bit units. if the higher 8 bits of the pmdl register are used as pmdlh, and the lower 8 bits as pmdll, however, pmdlh and pmdll can be read or written in 8-bit or 1-bit units. pmdl7 output mode input mode pmdln 0 1 controls input/output mode (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: pmdl ffff f024h, pmdll ffff f024h, pmdlh fffff025h pmdl15 pmdlh (pmdlh note ) (pmdll) pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 note when reading or writing bits 8 to 15 of the pmdl regist er in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmdlh register. (c) port mode control register dl (pmcdl) this is a 16-bit register that spec ifies the port mode or control mode. it can be read or written only in 16-bit units. if the higher 8 bits of the pmcdl register are us ed as pmcdlh, and the lower 8 bits as pmcdll, however, pmcdlh and pmcdll can be read or written in 8-bit units. i/o port adn output (address/data bus input/output) pmcdln 0 1 specifies operation mode of pdln pin (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset: 0000h r/w address: pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h pmcdl15 pmcdl (pmcdlh note ) (pmcdll) pmcdl14pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 note when reading or writing bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmcdlh register. caution do not specify ad8 to ad1 5 when the smsel bit of the eximc register = 1 (separate mode) and when the bs30 to bs00 bits of the bsc register = 0 (8-bit bus width). chapter 4 port functions user?s manual u15905ej2v1ud 169 (3) block diagram figure 4-33. block diagram of pdl0 to pdl15 internal bus wr pmc rd address output of ad0 to ad15 input enable signal of ad0 to ad15 input of ad0 to ad15 output enable signal of ad0 to ad15 output buffer off signal wr port pdl0/ad0 to pdl15/ad15 pmcdln output latch (pdln) selector selector selector selector wr pm pmdln pmcdl pdl pmdl remarks 1 . pdl: port register dl pmdl: port mode register dl pmcdl: port mode control register dl output buffer off signal: signal that is active in idle/stop mode 2. n = 0 to 15 chapter 4 port functions user?s manual u15905ej2v1ud 170 other bits (register) intr00 (intr0), intf00 (intf0) intr01 (intr0), intf01 (intf0) ? intr02 (intr0), intf02 (intf0) ? intr03 (intr0), intf00 (intf0) ? intr04 (intr0), intf04 (intf0) ? intr05 (intr0), intf05 (intf0) ? pf21 = don?t care (pf2) pf22 = don?t care (pf2) ? ? pf31 = 0 (pf3) pf31 = don?t care (pf3) pf32 = don?t care (pf3) ? pf41 = don't care (pf4) pf41 = 1 (pf4) pf42= don?t care (pf4) pf42 = 1 (pf4) pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? ? pfc30 = 0 pfc30 = 1 pfc31 = 0 pfc31 = 1 ? ? pfc41 = 0 pfc41 = 1 pfc42 = 0 pfc42 = 1 pmcnx bit of pmcn register pmc00 = 1 pmc01 = 1 pmc01 = 1 pmc02 = 1 pmc02 = 1 pmc03 = 1 pmc03 = 1 pmc04 = 1 pmc04 = 1 pmc05 = 1 pmc20 = 1 pmc21 = 1 pmc22 = 1 pmc30 = 1 pmc30 = 1 pmc31 = 1 pmc31 = 1 pmc32 = 1 pmc40 = 1 pmc41 = 1 pmc41 = 1 pmc42 = 1 pmc42 = 1 pmnx bit of pmn register pm00 = setting not needed pm01 = setting not needed pm01 = setting not needed pm02 = setting not needed pm02 = setting not needed pm03 = setting not needed pm03 = setting not needed pm04 = setting not needed pm04 = setting not needed pm05 = setting not needed pm20 = setting not needed pm21 = setting not needed pm22 = setting not needed pm30 = setting not needed pm30 = setting not needed pm31 = setting not needed pm31 = setting not needed pm32 = setting not needed pm40 = setting not needed pm41 = setting not needed pm41 = setting not needed pm42 = setting not needed pm42 = setting not needed pnx bit of pn register p00 = setting not needed p01 = setting not needed p01 = setting not needed p02 = setting not needed p02 = setting not needed p03 = setting not needed p03 = setting not needed p04 = setting not needed p04 = setting not needed p05 = setting not needed p20 = setting not needed p21 = setting not needed p22 = setting not needed p30 = setting not needed p30 = setting not needed p31 = setting not needed p31 = setting not needed p32 = setting not needed p40 = setting not needed p41 = setting not needed p41 = setting not needed p42 = setting not needed p42 = setting not needed i/o input input input input input input input input input input input output i/o input input output output i/o input output i/o i/o i/o alternate function name nmi intp0 ti2 intp1 ti3 intp2 ti4 intp3 ti5 intp4 si4 so4 si1 rxd0 so1 txd0 sck1 si0 so0 sda note sck0 scl note table 4-18. using alternate function of port pins (1/6) pin name p00 p01 p02 p03 p04 p05 p20 p21 p22 p30 p31 p32 p40 p41 p42 note pd703201y, 703204y, 70f3201y, and 70f3204y only sck4 chapter 4 port functions user?s manual u15905ej2v1ud 171 other bits (register) eti0 = 0 (tmc01), note eti0 = 1 (tmc01), note eclr0 = 1 (tmc01), note ? ? eti1 = 0 (tmc11), note eti1 = 1 (tmc11), note eclr1 = 1 (tmc11), note ? ? ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? pfc44 = 0 pfc44 = 1 ? ? ? pfc46 = 0 pfc46 = 1 ? ? ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmc43 = 1 pmc43 = 1 pmc43 = 1 pmc44 = 1 pmc44 = 1 pmc45 = 1 pmc45 = 1 pmc45 = 1 pmc46 = 1 pmc46 = 1 ? ? ? ? ? ? ? ? ? ? ? pmnx bit of pmn register pm43 = setting not needed pm43 = setting not needed pm43 = setting not needed pm44 = setting not needed pm44 = setting not needed pm45 = setting not needed pm45 = setting not needed pm45 = setting not needed pm46 = setting not needed pm46 = setting not needed ? ? ? ? ? ? ? ? ? ? ? pnx bit of pn register p43 = setting not needed p43 = setting not needed p43 = setting not needed p44 = setting not needed p44 = setting not needed p45 = setting not needed p45 = setting not needed p45 = setting not needed p46 = setting not needed p46 = setting not needed p70 = setting impossible p71 = setting impossible p72 = setting impossible p73 = setting impossible p74 = setting impossible p75 = setting impossible p76 = setting impossible p77 = setting impossible p78 = setting impossible p79 = setting impossible p710 = setting impossible i/o input input input input output input input input input output input input input input input input input input input input input alternate function name intp00 ti0 tclr0 intp01 to0 intp10 ti1 tclr1 intp11 to1 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 table 4-18. using alternate function of port pins (2/6) pin name p43 p44 p45 p46 p70 p71 p72 p73 p74 p75 p76 p77 p78 p79 p710 note set the valid edge by using the timer n valid edge selection register (sesn). chapter 4 port functions user?s manual u15905ej2v1ud 172 other bits (register) ? ? ? ? ? ? ? note ? note intr92 (intr9), intf92 (intf9) note intr93 (intr9), intf93 (intf9) note ? note ? note ? note ? note ? pfcnx bit of pfcn register ? ? ? ? ? ? ? pfc90 = 0 pfc91 = 0 pfc92 = 0 pfc92 = 1 pfc93 = 0 pfc93 = 1 pfc94 = 0 pfc94 = 1 pfc95 = 0 pfc95 = 1 pfc96 = 0 pfc96 = 1 pfc97 = 0 pfc97 = 1 pfc98 = 0 pfc98 = 1 pmcnx bit of pmcn register ? ? ? ? ? ? ? pmc90 = 1 pmc91 = 1 pmc92 = 1 pmc92 = 1 pmc93 = 1 pmc93 = 1 pmc94 = 1 pmc94 = 1 pmc95 = 1 pmc95 = 1 pmc96 = 1 pmc96 = 1 pmc97 = 1 pmc97 = 1 pmc98 = 1 pmc98 = 1 pmnx bit of pmn register ? ? ? ? ? ? ? pm90 = setting not needed pm91 = setting not needed pm92 = setting not needed pm92 = setting not needed pm93 = setting not needed pm93 = setting not needed pm94 = setting not needed pm94 = setting not needed pm95 = setting not needed pm95 = setting not needed pm96 = setting not needed pm96 = setting not needed pm97 = setting not needed pm97 = setting not needed pm98 = setting not needed pm98 = setting not needed pnx bit of pn register p711 = setting impossible p712 = setting impossible p713 = setting impossible p714 = setting impossible p715 = setting impossible p80 = setting impossible p780 = setting impossible p90 = setting not needed p91 = setting not needed p92 = setting not needed p92 = setting not needed p93 = setting not needed p93 = setting not needed p94 = setting not needed p94 = setting not needed p95 = setting not needed p95 = setting not needed p96 = setting not needed p96 = setting not needed p97 = setting not needed p97 = setting not needed p98 = setting not needed p98 = setting not needed i/o input input input input input output output output output output input output input output output output output output output output output output input alternate function name ani11 ani12 ani13 ani14 ani15 ano0 ano1 a0 a1 a2 intp5 a3 intp6 a4 to2 a5 to3 a6 to4 a7 to5 a8 rxd1 table 4-18. using alternate function of port pins (3/6) pin name p711 p712 p713 p714 p715 p80 p81 p90 p91 p92 p93 p94 p95 p96 p97 p98 note to set the a0 to a15 pins, clear the pfc9 register to 0000h and set the pmc9 register to ffffh in 16-bit units. chapter 4 port functions user?s manual u15905ej2v1ud 173 other bits (register) note ? note ? note pf911 = don?t care (pf9) note pf912 = don?t care (pf9) note ? note pf914 = don?t care (pf9) note pf915 = don?t care (pf9) pfcnx bit of pfcn register pfc99 = 0 pfc99 = 1 pfc910 = 0 pfc910 = 1 pfc911 = 0 pfc911 = 1 pfc912 = 0 pfc912 = 1 pfc913 = 0 pfc913 = 1 pfc914 = 0 pfc914 = 1 pfc915 = 0 pfc915 = 1 pmcnx bit of pmcn register pmc99 = 1 pmc99 = 1 pmc910 = 1 pmc910 = 1 pmc911 = 1 pmc911 = 1 pmc912 = 1 pmc912 = 1 pmc913 = 1 pmc913 = 1 pmc914 = 1 pmc914 = 1 pmc915 = 1 pmc915 = 1 pmnx bit of pmn register pm99 = setting not needed pm99 = setting not needed pm910 = setting not needed pm910 = setting not needed pm911 = setting not needed pm911 = setting not needed pm912 = setting not needed pm912 = setting not needed pm913 = setting not needed pm913 = setting not needed pm914 = setting not needed pm914 = setting not needed pm915 = setting not needed pm915 = setting not needed pnx bit of pn register p99 = setting not needed p99 = setting not needed p910 = setting not needed p910 = setting not needed p911 = setting not needed p911 = setting not needed p912 = setting not needed p912 = setting not needed p913 = setting not needed p913 = setting not needed p914 = setting not needed p914 = setting not needed p915 = setting not needed p915 = setting not needed i/o output output output input output output output output output input output output output output alternate function name a9 txd1 a10 si2 a11 so2 a12 sck2 a13 si3 a14 so3 a15 sck3 table 4-18. using alternate function of port pins (4/6) pin name p99 p910 p911 p912 p913 p914 p915 note to set the a0 to a15 pins, clear the pfc9 register to 0000h and set the pmc9 register to ffffh in 16-bit units. chapter 4 port functions user?s manual u15905ej2v1ud 174 other bits (register) ? ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmccm0 = 1 pmccm1 = 1 pmccm2 = 1 pmccm3 = 1 pmccs0 = 1 pmccs1 = 1 pmccs2 = 1 pmccs3 = 1 pmcct0 = 1 pmcct1 = 1 pmcct4 = 1 pmcct6 = 1 pmnx bit of pmn register pmcm0 = setting not needed pmcm1 = setting not needed pmcm2 = setting not needed pmcm3 = setting not needed pmcs0 = setting not needed pmcs1 = setting not needed pmcs2 = setting not needed pmcs3 = setting not needed pmct0 = setting not needed pmct1 = setting not needed pmct4 = setting not needed pmct6 = setting not needed pnx bit of pn register pcm0 = setting not needed pcm1 = setting not needed pcm2 = setting not needed pcm3 = setting not needed pcs0 = setting not needed pcs1 = setting not needed pcs2 = setting not needed pcs3 = setting not needed pct0 = setting not needed pct1 = setting not needed pct4 = setting not needed pct6 = setting not needed i/o input output output input output output output output output output output output alternate function name wait clkout hldak hldqr cs0 cs1 cs2 cs3 wr0 wr1 rd astb table 4-18. using alternate function of port pins (5/6) pin name pcm0 pcm1 pcm2 pcm3 pcs0 pcs1 pcs2 pcs3 pct0 pct1 pct4 pct6 chapter 4 port functions user?s manual u15905ej2v1ud 175 other bits (register) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmcdh0 = 1 pmcdh1 = 1 pmcdh2 = 1 pmcdh3 = 1 pmcdh4 = 1 pmcdh5 = 1 pmcdh6 = 1 pmcdh7 = 1 pmcdl0 = 1 pmcdl1 = 1 pmcdl2 = 1 pmcdl3 = 1 pmcdl4 = 1 pmcdl5 = 1 pmcdl6 = 1 pmcdl7 = 1 pmcdl8 = 1 pmcdl9 = 1 pmcdl10 = 1 pmcdl11 = 1 pmcdl12 = 1 pmcdl13 = 1 pmcdl14 = 1 pmcdl15 = 1 pmnx bit of pmn register pmdh0 = setting not needed pmdh1 = setting not needed pmdh2 = setting not needed pmdh3 = setting not needed pmdh4 = setting not needed pmdh5 = setting not needed pmdh6 = setting not needed pmdh7 = setting not needed pmdl0 = setting not needed pmdl1 = setting not needed pmdl2 = setting not needed pmdl3 = setting not needed pmdl4 = setting not needed pmdl5 = setting not needed pmdl6 = setting not needed pmdl7 = setting not needed pmdl8 = setting not needed pmdl9 = setting not needed pmdl10 = setting not needed pmdl11 = setting not needed pmdl12 = setting not needed pmdl13 = setting not needed pmdl14 = setting not needed pmdl15 = setting not needed pnx bit of pn register pdh0 = setting not needed pdh1 = setting not needed pdh2 = setting not needed pdh3 = setting not needed pdh4 = setting not needed pdh5 = setting not needed pdh6 = setting not needed pdh7 = setting not needed pdl0 = setting not needed pdl1 = setting not needed pdl2 = setting not needed pdl3 = setting not needed pdl4 = setting not needed pdl5 = setting not needed pdl6 = setting not needed pdl7 = setting not needed pdl8 = setting not needed pdl9 = setting not needed pdl10 = setting not needed pdl11 = setting not needed pdl12 = setting not needed pdl13 = setting not needed pdl14 = setting not needed pdl15 = setting not needed i/o output output output output output output output output i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o alternate function name a16 a17 a18 a19 a20 a21 a22 a23 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 table 4-18. using alternate function of port pins (6/6) pin name pdh0 pdh1 pdh2 pdh3 pdh4 pdh5 pdh6 pdh7 pdl0 pdl1 pdl2 pdl3 pdl4 pdl5 pdl6 pdl7 pdl8 pdl9 pdl10 pdl11 pdl12 pdl13 pdl14 pdl15 chapter 4 port functions user?s manual u15905ej2v1ud 176 4.4 cautions the operation of a port differs depending on whether the port is in the input or output mode, as described below. 4.4.1 writing data to i/o port (1) in output mode a value can be written to the output latch by using a tr ansfer instruction. the cont ents of the output latch are output from the pin. once data has been written to the output latch, it is reta ined until new data is written to the output latch. (2) in input mode a value can be written to the output latch by using a tran sfer instruction. because the output buffer is off, however, the status of the pin does not change. once data has been written to the output latch, it is retained until new data is wri tten to the output latch. caution a 1-bit memory manipulation instruction ma nipulates 1 bit but accesses a port in 8-bit units. if this instruction is executed to manipulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in th e input mode, in addition to the bit to be manipulated, become undefined. 4.4.2 reading data from i/o port (1) in output mode the contents of the output latch can be read by using a tr ansfer instruction. the cont ents of the output latch do not change. (2) in input mode the status of the pin can be read by using a transfer instruction. the contents of the out put latch do not change. user?s manual u15905ej2v1ud 177 chapter 5 bus control function the v850es/sa2 and v850es/sa3 are provided with an external bus interface function by which external memories such as rom and ra m, and i/o can be connected. 5.1 features output is selectable from a multiplexed bus with a mi nimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles. four-space chip select signal output function 8-bit/16-bit data bus selectable (for each area selected by chip select function) wait function ? programmable wait function of up to 7 states (selec table for each area selected by chip select function) ? external wait function using wait pin idle state function bus hold function 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins (multiplexed bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus a16 to a23 note pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock cs0 to cs3 pcs0 to pcs3 output chip select signal wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control note a16 to a21 in the v850es/sa2 chapter 5 bus control function user?s manual u15905ej2v1ud 178 table 5-2. external control pins (separate bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a23 note pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock cs0 to cs3 pcs0 to pcs3 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal hldrq pcm3 input hldak pcm2 output bus hold control note a16 to a21 in the v850es/sa2 5.2.1 pin status when internal rom, internal ram, or internal peripheral i/o is accessed when the internal rom, internal ram, or internal periphe ral i/o is accessed, the status of each pin is as follows. table 5-3. pin status when inte rnal rom, internal ram, or inte rnal peripheral i/o is accessed separate mode multiplexed bus mode address bus (a23 to a0) undefined address bus (a23 to a16) undefined data bus (ad15 to ad0) hi-z data bus (ad15 to ad0) undefined control signal inactive control signal inactive caution when the internal rom area is write-a ccessed, the addresses, data, and control signals are activated in the same way as acce ss to the external memory area. 5.2.2 pin status in each operation mode for the pin status of the v850es/sa2 and v 850es/sa3 in each operation mode, refer to 2.2 pin status . chapter 5 bus control function user?s manual u15905ej2v1ud 179 5.3 memory block function the 64 mb memory space is divided into memory blocks of (lower) 2 mb, 2mb, 4mb, and 8mb. the programmable wait function and bus cycl e operation mode for each of these bloc ks can be independen tly controlled in one-block units. figure 5-1. data memory map (80 kb) use prohibited external memory area note 1 (8 mb) internal rom area note 2 (1 mb) external memory area (1 mb) internal ram area (16 kb) internal peripheral i/o area (4 kb) use prohibited external memory area (4 mb) external memory area (2 mb) (2 mb) cs0 cs1 cs2 cs3 3ffffffh 3fec000h 3febfffh 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 3ffffffh 3fff000h 3ffefffh 3ffb000h 3ffafffh 3fec000h 01fffffh 0100000h 00fffffh 0000000h notes 1. this area is the 4 mb space of 080000 0h to 0bfffffh in the v 850es/sa2 (0c00000h to 0ffffffh are the image of 0800000h to 0bfffffh). 2. this area is an external memory area in the case of a data write access. chapter 5 bus control function user?s manual u15905ej2v1ud 180 5.3.1 chip select control function of the 64 mb (linear) address space, the lower 16 mb (0 000000h to 0ffffffh) include four chip select functions, cs0 to cs3. the areas that can be selected by cs0 to cs3 are fixed. by using these chip select functions, the memory bloc k can be divided to enable effective use of the memory space. the allocation of the memory blocks is shown in the table below. v850es/sa2 v850es/sa3 cs0 0000000h to 01fffffh (2 mb) 0000000h to 01fffffh (2 mb) cs1 0200000h to 03fffffh (2 mb) 0200000h to 03fffffh (2 mb) cs2 0400000h to 07fffffh (4 mb) 0400000h to 07fffffh (4 mb) cs3 0800000h to 0bfffffh (4 mb) 0800000h to 0ffffffh (8 mb) 5.4 external bus interface mode control function the v850es/sa2 and v850es/sa3 include the following two external bus interface modes. ? multiplexed bus mode ? separate bus mode these two modes can be selected by using the extern al bus interface mode control register (eximc). (1) external bus interface mode control register (eximc) this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. 0 multiplexed bus mode separate bus mode smsel 0 1 mode selection eximc 0 0 0 0 0 0 smsel after reset: 00h r/w address: ffffffbeh chapter 5 bus control function user?s manual u15905ej2v1ud 181 5.5 bus access 5.5.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 or 2 3 + n note instruction fetch (branch) 2 1 or 2 3 + n note operand data access 3 1 3 + n note note 2 + n clocks (n: number of wait states ) when the separate bus mode is selected. remark unit: clocks/access 5.5.2 bus size setting function the bus size of each external memory area selected by csn can be set (to 8 bits or 16 bits) by using the bsc register. the external memory area of t he v850es/sa2 (010 0000h to 0bfffffh) is selected by cs0 to cs3. the external memory area of t he v850es/sa3 (010 0000h to 0ffffffh) is selected by cs0 to cs3. (1) bus size configuration register (bsc) this register can be read or written in 16-bit units. caution write to the bsc register after reset, and then do not change the set values. also, do not access an external memory area other than th e one for this initialization routine until the initial settings of the bsc register are co mplete. however, external memory areas whose initial settings are complete may be accessed. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 bs30 0 0 1 bs20 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 data bus width of csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 csn signal cs2 cs1 caution be sure to set bits 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. chapter 5 bus control function user?s manual u15905ej2v1ud 182 5.5.3 access by bus size the v850es/sa2 and v850es/sa3 access the internal peri pheral i/o and external memory in 8-bit, 16-bit, or 32- bit units. the bus size is as follows. ? the bus size of the internal peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/sa2 and v850es/sa3 support only the little endian format. figure 5-2. little endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus chapter 5 bus control function user?s manual u15905ej2v1ud 183 (2) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus chapter 5 bus control function user?s manual u15905ej2v1ud 184 (3) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u15905ej2v1ud 185 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u15905ej2v1ud 186 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u15905ej2v1ud 187 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u15905ej2v1ud 188 5.6 wait function 5.6.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each cs space. the number of wait states can be programmed by using data wait control register 0 (dwc0). immediately after system reset, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. cautions 1. the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the inte rnal peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initia lization routine until the initial settings of the dwc0 register ar e complete. however, external memory areas whose initial settings are complete may be accessed. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 dwc0 dw32 dw12 dw31 dw11 dw30 dw10 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 number of wait states inserted in csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 csn signal csn signal cs2 cs1 caution be sure to clear bits 15, 11, 7, and 3 to 0. chapter 5 bus control function user?s manual u15905ej2v1ud 189 5.6.2 external wait function to synchronize an extremely slow external device, i/o, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). access to each area of the internal rom, internal ram, and internal periphera l i/o is not subject to control by the external wait function, in the same man ner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle in the multiplexed bus mode. in the separate bus mode, it is sampled at the rising edge of the clock immediately after the t1 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. chapter 5 bus control function user?s manual u15905ej2v1ud 190 5.6.3 relationship between programm able wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specifi ed by the set value of the programmable wait and the wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait and the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-3. example of wait insertion (a) in separate bus mode t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. (b) in multiplexed bus mode clkout t1 t2 tw tw tw t3 wait pin wait by wait pin programmable wait wait control remark the circles indicate the sampling timing. chapter 5 bus control function user?s manual u15905ej2v1ud 191 5.6.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control register (awc). address wait insertion is set for each chip select area (cs0 to cs3). if an address setup wait is inserted, it seems that the high-clock period of t1 state is extended by 1 clock. if an address hold wait is inserted, it seems that the low- clock period of t1 state is extended by 1 clock. (1) address wait control register (awc) this register can be read or written in 16-bit units. after reset: ffffh r/w address: fffff488h 1 ahw3 ahwn 0 1 not inserted inserted awc 1 asw3 1 ahw2 1 asw2 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 specifies insertion of address hold wait (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted specifies insertion of address setup wait (n = 0 to 3) cs0 cs3 csn signal cs2 cs1 caution be sure to set bits 15 to 8 to 1. chapter 5 bus control function user?s manual u15905ej2v1ud 192 5.7 idle state insertion function to facilitate interfacing with low-speed memories, one idle state (ti) can be inserted a fter the t3 state in the bus cycle that is executed for each space selected by the chip select function in the multiplexed address/data bus mode. in the separate bus mode, one idle state (ti) can be inserted after the t2 state. by inserting an idle state, the data output float delay time of the memory can be secured du ring read access (an idle state cannot be inserted during write access). whether the idle state is to be inserted can be prog rammed by using the bus cycle control register (bcc). an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) this register can be read or written in 16-bit units. cautions 1. the internal rom, internal ram, and intern al peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area ot her than the one for this in itialization routine until the initial settings of the bcc register are comp lete. however, external memory areas whose initial settings are complete may be accessed. after reset: aaaah r/w address: fffff48ah 1 bc31 bcn1 0 1 not inserted i nserted bcc 0 0 1 bc21 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 csn signal cs2 cs1 caution be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0. chapter 5 bus control function user?s manual u15905ej2v1ud 193 5.8 bus hold function 5.8.1 functional outline the hldak and hldrq functions are valid if the pc m2 and pcm3 pins are set in the control mode. when the hldrq pin is asserted (low level), indicating th at another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until a peripheral i/o register or the ex ternal memory is accessed. the bus hold status is indicated by assertion of the hldak pin (low level). the bus hold function enables the configuration mult i-processor type systems in which two or more bus masters exist. note that the bus hold request is not acknowledged during a multiple-acce ss cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing in which bus hold request not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access chapter 5 bus control function user?s manual u15905ej2v1ud 194 5.8.2 bus hold procedure the bus hold status transition procedure is shown below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.8.3 operation in power save mode because the internal system clock is stopped in the so ftware stop and idle modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deassert ed, the hldak pin is also deasserted, and the bus hold status is cleared. chapter 5 bus control function user?s manual u15905ej2v1ud 195 5.9 bus priority bus hold, instruction fetch (branch), instruction fetch (s uccessive), and operand data accesses are executed in the external bus cycle. bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-4. bus priority priority external bus cycle bus master high bus hold external device dma transfer dmac operand data access cpu instruction fetch (branch) cpu low instruction fetch (successive) cpu 5.10 boundary operation conditions 5.10.1 program space (1) if a branch instruction exists at t he upper limit of the internal ram area, a prefetch operation straddling over the internal peripheral i/o area (invalid fetch) does not occur. (2) instruction execution to the external memory area ca nnot be continued without a br anch from the internal rom area to the external memory area. 5.10.2 data space the v850es/sa2 and v850es/sa3 have an address misalign function. with this function, data can be placed at all addresses, rega rdless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (1) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (2) word-length data access (a) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (b) a halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10. chapter 5 bus control function user?s manual u15905ej2v1ud 196 5.11 bus timing figure 5-4. multiplexed bus read timi ng (bus size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a23 to a16 astb cs3 to cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-5. multiplexed bus read timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a23 to a16, ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function user?s manual u15905ej2v1ud 197 figure 5-6. multiplexed bus write ti ming (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a23 to a16 astb cs3 to cs0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active figure 5-7. multiplexed bus write timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a23 to a16, ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 wr1, wr0 chapter 5 bus control function user?s manual u15905ej2v1ud 198 figure 5-8. multiplexed bus hold timi ng (bus size: 16 bits, 16-bit access) t1 a1 undefined a1 a2 t2 t3 ti note th th th th ti note t1 t2 t3 d1 clkout hldrq hldak a23 to a16 astb cs3 to cs0 ad15 to ad0 rd undefined undefined undefined a2 d2 1111 1111 note this idle state (ti) does not de pend on the bcc register settings. remarks 1. refer to table 2-3 for the pin statuses in the bus hold mode. 2. the broken lines indicate high impedance. chapter 5 bus control function user?s manual u15905ej2v1ud 199 figure 5-9. separate bus read timi ng (bus size: 16 bits, 16-bit access) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a23 to a0 cs3 to cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-10. separate bus read timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a23 to a0 cs3 to cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function user?s manual u15905ej2v1ud 200 figure 5-11. separate bus write timi ng (bus size: 16 bits, 16-bit access) t1 a1 11 00 00 00 11 11 11 11 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a23 to a0 cs3 to cs0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active remark the broken lines indicate high impedance. figure 5-12. separate bus write timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a23 to a0 cs3 to cs0 wait ad7 to ad0 wr1, wr0 11 10 10 10 11 11 11 11 remark the broken lines indicate high impedance. chapter 5 bus control function user?s manual u15905ej2v1ud 201 figure 5-13. separate bus hold ti ming (bus size: 8 bits, write) clkout t1 t2 a1 d1 d2 undefined a2 undefined 11 11 10 d3 a3 t1 t2 th ti ? ti ? th th th t1 t2 hldrq hldak a23 to a0 ad7 to ad0 wr1, wr0 cs3 to cs0 11 10 11 10 1111 1111 11 note this idle state (ti) does not de pend on the bcc register settings. remark the broken lines indicate high impedance. figure 5-14. address wait timing (separate bus read, bus size: 16 bits, 16-bit access) tasw t1 tahw t2 clkout astb a23 to a0 cs3 to cs0 wait ad15 to ad0 rd d1 a1 t1 t2 clkout astb a23 to a0 cs3 to cs0 wait ad15 to ad0 rd d1 a1 remarks 1. tasw (address setup wait): image of hi gh-level width of t1 state expanded. 2. tahw (address hold wait): image of lo w-level width of t1 state expanded. 3. the broken lines indicate high impedance. user?s manual u15905ej2v1ud 202 chapter 6 clock generation function 6.1 overview the features of the clock generat ion function are as follows. main clock oscillator (f x ) ? 2 to 20 mhz (at 2.2 to 2.7 v operation) subclock oscillator (f xt ) ? 32.768 khz generation of internal system clock (f clk ) ? seven steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) generation of peripheral clock clock output function (clkout) chapter 6 clock generation function user?s manual u15905ej2v1ud 203 6.2 configuration figure 6-1. clock generator frc bit mfrc bit ck3 to ck0 bits stop mode subclock oscillator port cm wdt clock control prescaler 1 prescaler 2 idle control idle control halt control halt mode cpu clock a/ d converter rtc clock peripheral clock wdt clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control xt1 xt2 clkout x1 x2 idle selector f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xt f xx to f xx /512 f x /2 6 to f x /2 9 f xt f xt f x f xx f xw remark f x : main clock oscillation frequency f xx : main clock frequency f xt : subclock frequency f cpu : cpu clock frequency f clk : internal system clock frequency f xw : watchdog timer clock frequency chapter 6 clock generation function user?s manual u15905ej2v1ud 204 (1) main clock oscillator this circuit oscillates the following frequency (f x ): ? 2 to 20 mhz (at 2.2 to 2.7 v operation) (2) subclock oscillator this circuit oscillates a frequency of 32.768 khz (f xt ). (3) main clock resonator stop control this circuit generates a control signal that st ops oscillation of the main clock resonator. it stops the oscillation of the main clock resonator in the software stop mode or when the mck bit = 1 (valid only when the cls bit = 1). (4) prescaler 1 this circuit generates the clock (f xx to f xx /512) to be supplied to the internal peripheral functions. the clock is supplied to the following blocks: tm0 to tm5, csi0 to csi4, uart0, uart1, i 2 c, adc, dac (5) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to t he selector that generat es the internal system clock (f clk ). f clk is the clock that is supplied to the cpu, in tc, dmac, and romc blocks, and can be output from the clkout pin. (6) prescaler 3 this circuit divides the clock (f x ) generated by the main resonator to a specific frequency (32.768 khz) and supplies it to the rtc and adc. for details, refer to 6.5 prescaler 3 . (7) watchdog timer clock control this circuit generates the clock (f xw ) to be supplied to the watchdog timer. the watchdog timer is used alternately as the oscillation stabilization timer, so the s ource clock is automatically switched according to the operation status shown below. ? from software stop mode or reset pin input to when oscillation stabilization time has been counted: f x ? other than above: f xx chapter 6 clock generation function user?s manual u15905ej2v1ud 205 6.3 control registers (1) processor clock control register (pcc) the processor clock control register (pcc) is a special regist er. data can be written to it only in combination of specific sequences (refer to 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. the cls bit is a read-only bit. frc used not used frc 0 1 selects internal feedback resistor of subclock pcc mck mfrc cls note ck3 ck2 ck1 ck0 operating stopped mck 0 1 operation of main clock used not used mfrc 0 1 selects internal feedback resistor of main clock after reset: 03h r/w address: fffff828h main clock operation subclock operation cls 0 1 status of cpu clock (f cpu ) f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 setting prohibited f xt (subclock: 32.768 khz) ck2 0 0 0 0 1 1 1 x selects clock ( f clk /f cpu ) ck1 0 0 1 1 0 0 1 x ck0 0 1 0 1 0 1 x x ck3 0 0 0 0 0 0 0 1 ? even if the mck bit is set to 1 while the system is operating with the main clock as the cpu clock, the operation of the main system clock does not stop. it stops after the cpu clock has been changed to the subclock. ? when the main clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. <6> <4> <3> note the cls bit is a read-only bit. caution do not change the cpu clock (by using th e ck2 to ck0 bits of the pcc register) while clkout is being output. remark x: don?t care. chapter 6 clock generation function user?s manual u15905ej2v1ud 206 examples of settings to change between the main clock and subclock are shown below (a) example of setting when changing from main clock to subclock <1> checking internal system clock: check if the following cond ition is satisfied. ? internal system clock (f clk ) > subclock (32.768 khz) 4 if this condition is not satisfied, change the setting of the ck2 to ck0 bits so that the condition is satisfied. at this time, do not change the setting of the ck3 bit. <2> ck3 bit ?1?: use of a bit manipulation instruction is recommended. do not change the setting of the ck2 to ck0 bits. <3> subclock operation: the following time is required between when the ck3 bit is set and when the subclock operation is started: ? maximum: (1/subclock frequency) therefore, read the cls bit and c onfirm that the subclock operation has started. <4> mck ?1?: set mck to 1 only when stopping the main clock. (b) example of setting when changing subclock to main clock <1> mck ?0?: oscillation of the main clock is started. <2> software wait: insert wait states by program and wait until the oscillat ion stabilization time of the main clock elapses. <3> ck3 ?0?: use of a bit manipulation instruction is recommended. do not change the setting of the ck2 to ck0 bits. <3> main clock operation: the following time is r equired between when the ck3 bit is set and when the main clock specified by the ck2 to ck0 bits is selected. ? maximum: (1/subclock frequency) therefore, read the cls bit and confir m that the main clock operation has started. chapter 6 clock generation function user?s manual u15905ej2v1ud 207 (2) power save control register (psc) the power save control register (psc) is a special regi ster. data can be written to this register only in combination of specific sequences (refer to 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. 0 psc 0 0 0 0 0 stp 0 normal mode idle/software stop mode stp 0 1 setting of idle/software stop mode after reset: 00h r/w address: fffff1feh < > (3) power save mode register (psmr) this is an 8-bit register that cont rols the operation status and clock operation in the power save mode. it can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. 0 idle mode software stop mode psm 0 1 specifies operation in software standby mode (valid when bit 1 (stp) of the psc register is set to 1) psmr 0 0 0 0 0 0 psm after reset: 00h r/w address: fffff820h < > cautions 1. be sure to clear bits 1 to 7 of the psmr register to 0. 2. the psm bit is valid only when the stp bit of the psc register is set to 1. (4) oscillation stabilization time selection register (osts) this is an 8-bit register that controls the oper ation status and clock in the power save mode. refer to 10.3 (1) oscillation stabilizatio n time selection register (osts) . chapter 6 clock generation function user?s manual u15905ej2v1ud 208 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock cls bit = 0 mck bit = 0 cls bit = 1 mck bit = 0 cls bit = 1 mck bit = 1 <1> <2> <3> <4> <5> <6> <7> <6> <7> main resonator (f x ) sub-resonator (f xt ) cpu clock (f cpu ) internal system clock (f clk ) peripheral clock (f xx to f xx /512) wdt clock (f xw ) note rtc clock (sub) rtc clock (main) note the watchdog timer clock (f xw ) is operable but it stops operating in the watchdog timer if the cls bit of the processor clock control register (pcc) is set to 1. remarks cls bit: bit 6 of pcc register mck bit: bit 4 of pcc register : operable : stops <1>: reset pin input <2>: during oscillation stabilization time count <3>: halt mode <4>: idle mode <5>: software stop mode <6>: subclock operation mode <7>: sub-idle mode 6.4.2 clock output function the clock output function allows the clkout pin to output the internal system clock (f clk ). the internal system clock (f clk ) is selected by using the ck3 to ck0 bits of the processor clock control register (pcc). the clkout pin functions alternately as the pcm1 pi n and operates as a clock output pin when the control register of port cm is manipulated (refer to 4.3.9 port cm ). the status of the clkout pin is the sa me as the internal system clock in ta ble 6-1, and can output the clock when it is (operable). when it is (stops), it outputs a low level. immediately after reset <1> and in the operation status of <2>, the alternate function of the cl kout pin is used (pcm1: input mode), and therefore the pin goes into a high- impedance state. chapter 6 clock generation function user?s manual u15905ej2v1ud 209 6.5 prescaler 3 prescaler 3 has the following functions. ? generation of clock for count clock of watch timer (source clock: main clock oscillation) ? generation of clock for count clock of a/d co nverter (source clock: main clock oscillator) ? interval timer (intbrg) figure 6-2. block diagram of prescaler 3 selector f x f x /8 f x /4 f x /2 f x bgcs0 bgcs1 todis ce 3-bit prescaler 8-bit counter output control prscm: prscm0 to prscm7 match f bgcs f brg intbrg prescaler mode register (wtm) remark f brg : prescaler 3 clock frequency f x : main clock oscillation frequency chapter 6 clock generation function user?s manual u15905ej2v1ud 210 6.5.1 control register (1) prescaler mode register (prsm) the prsm register controls generation of t he clock of the watch timer and a/d converter. this register can be read or written in 8-bit or 1-bit units. 0 prsm 0 0 ce 0 todis bgcs1 bgcs0 fixed to 0 operates fixed to 0 ce 0 1 1 todis x 0 1 baud rate output fixed to 0 operates operates baud rate interrupt signal (intbrg) f x f x /2 f x /4 f x /8 10 mhz 100 ns 200 ns 400 ns 800 ns 4 mhz 250 ns 500 ns 1 s 2 s bgcs1 0 0 1 1 bgcs0 0 1 0 1 selects input clock (f brgs ) after reset: 00h r/w address: fffff8b0h cautions 1. do not change the values of bgcs1 and bgcs0 during transmission/reception. 2. set the prsm register before setting the ce bit to 1. 3. set the prsm and prscm registers in a ccordance with the main clock frequency to be used, so that the frequency of f brg is 32.768 khz. chapter 6 clock generation function user?s manual u15905ej2v1ud 211 (2) prescaler compare register (prscm) this is an 8-bit compare register. it can be read or written in 8-bit or 1-bit units. prscm7 prscm prscm6 prscm5 prscm4 prscm3 prscm2 prscm1 prscm0 after reset: 00h r/w address: fffff8b1h cautions 1. do not change the value of the prscm register durin g transmission/reception. 2. set the prscm register before setting the ce bit of the prsm register to 1. 3. set the prsm and prscm registers in a ccordance with the main clock frequency to be used, so that the frequency of f brg is 32.768 khz. 6.5.2 generation of clock (1) count clock of watch timer the clock (f brg ) input to the watch timer can be correct ed to 32.768 khz or equivalent frequency. the relationship between the main clock oscillation frequency (f x ), the set value of input clock selection bit bgcsn (m), the set value of the prcsm register (n), and the output clock (f brg ) is as follows: example : where f x = 4.00 mhz, m = 0 (bgcs1 = bgcs = 0), n = 3dh, f brg = 32.768 khz f brg = f x /(2 m n 2) remark f brg : count clock n: value of compare register in prescaler 3 (1 to ffh) n = 256 if the value of the compare register is ?00h?. (2) interval timer this timer generates a baud rate interrupt re quest (intbrg) at preset time intervals. the interval time can be set by using the bgcs1 and bg cs0 bits of the prescaler mode register (prsm) and the prescaler compare register (prscm). the interval time can be calculated by the following expression. interval time = f x /(2 m n) user?s manual u15905ej2v1ud 212 chapter 7 16-bit timer/event counters 0 and 1 7.1 features 16-bit timer/event counters 0 and 1 ca n perform the following operations. ? interval timer function ? pwm output ? external signal cycle measurement 7.2 functional overview ? 16-bit timer/counter ? capture/compare common registers: 2 2 channels ? interrupt request sources ? capture/match interrupt requests: 2 2 channels ? overflow interrupt requests: 1 2 channels ? timer/counter count clock sources: 2 (selection of external pulse input or internal system clock division) ? either free-running mode or overflow stop mode can be selected as the operation mode when the timer/counter overflows ? timer/counter can be cleared by a match of the timer/counter and a compare register ? external pulse outputs: 1 2 channels chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 213 7.3 configuration table 7-1. 16-bit timer/event counter configuration timer count clock register read/write generated interrupt signal capture trigger timer output s/r tm0 read intovf0 ? ? cc00 read/write intcc00 intp00 to0 (s) cc01 read/write intcc01 intp01 to0 (r) tm1 read intovf1 ? ? cc10 read/write intcc10 intp10 to1 (s) tm0, tm1 f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256 cc11 read/write intcc11 intp11 to1 (r) remark f xx : main clock s/r: set/reset figure 7-1. block diagram of 16-bit timer/event counter r note q sq tmn (16 bits) ccn0 ccn1 intovfn intccn0 intpn1 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx tin/intpn0/tclrn intccn1 ton clear & start selector selector f xx note reset priority remarks 1. n = 0, 1 2. f xx : main clock chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 214 (1) timers 0 and 1 (tm0 and tm1) tmn functions as a 16-bit free-running timer or as an ev ent counter for an external signal. besides being used for cycle measurement, tmn can be used for pulse output (n = 0, 1). tmn is read-only, in 16-bit units. cautions 1. the tmn register can only be read. if the tmn register is written, the subsequent operation is undefined. 2. if the tmcaen bit of the tmcn0 regist er is cleared (0), a reset is performed asynchronously. tm1 fffff610h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tm0 fffff600h 0000h address after reset 0 tmn performs the count-up operations of an internal count clock or external count clock. timer start and stop are controlled by the tmcen bit of timer m ode control register n0 (tmcn0) (n = 0, 1). the internal or external count clock is selected by the etin bit of timer mode contro l register n1 (tmcn1) (n = 0, 1). (a) selection of the external count clock tmn operates as an event counter. when the etin bit of timer mode control register n1 (t mcn1) is set (1), tmn count s the valid edges of the external clock input (tin), synchronized with the internal count clock. the valid edge is specified by valid edge select register n (sesn) (n = 0, 1). caution when the intpn0/tin/tclrn pin is used as tin (external clock input pin), disable the intpn0 interrupt and set ccn0 to compare mode (n = 0, 1). (b) selection of the internal count clock tmn operates as a free-running timer. when the internal clock is specified as the count cloc k by timer mode control register n1 (tmcn1), tmn is counted up for each input clock cycle specified by the cs n0 to csn2 bits of the tmcn0 register (n = 0, 1). division by the prescaler can be sele cted for the count clock from among f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, and f xx /256 by the tmcn0 register (f xx : internal system clock). an overflow interrupt can be generated if the timer over flows. also, the timer can be stopped following an overflow by setting the ostn bit of the tmcn1 register to 1. caution the count clock cannot be ch anged while the timer is operating. chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 215 the conditions when the tmn register becomes 0000h are shown below. (a) asynchronous reset ? tmcaen bit of tmcn0 register = 0 ? after reset (b) synchronous reset ? tmcen bit of tmcn0 register = 0 ? the ccn0 register is used as a compare regist er, and the tmn and ccn0 registers match when clearing the tmn register is enabled (cclrn bit of the tmcn1 register = 1) (2) capture/compare registers n0 and n1 (ccn0 and ccn1) (n = 0, 1) these capture/compare registers ( n0 and n1) are 16-bit registers. they can be used as capture registers or compar e registers according to the cmsn0 and cmsn1 bit specifications of timer mode contro l register n1 (tmcn1) (n = 0, 1). these registers can be read or written in 16-bit units . (however, write operations can only be performed in compare mode.) these registers are cleared to 0000h after reset. cc1n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cc0n fffff602h, fffff604h fffff612h, fffff614h 0000h 0000h address after reset 0 remark n = 0, 1 (a) setting these registers as capture regi sters (cmsn0 and cmsn1 of tmcn1 = 0) when these registers are set as capture registers, the valid edges of the corresponding external interrupt signals intpn0 and intpn1 are detected as capture triggers. the timer tmn is synchronized with the capture trigger, and the value of tmn is latched in the ccn0 and ccn1 registers (capture operation). the valid edge of the intpn0 pin is specified (rising, falling, or both rising and falling edges) according to the iesn01 and iesn00 bits of the sesn register, a nd the valid edge of the intpn1 pin is specified according to the iesn11 and iesn10 bits of the sesn register (n = 0, 1). the capture operation is performed a synchronously to the count clock. the latched value is held in the capture register until anot her capture operation is performed (n = 0, 1). when the tmcaen bit of timer mode control register n0 (tmcn0) is 0, 0000h is read (n = 0, 1). if these registers are specified as c apture registers, an interrupt is gener ated by detecting the valid edge of signals intpn0 and intpn1 (n = 0, 1). caution if the capture operation conflicts with the timing of disabling the tmn register from counting (when the tmcen bit of the tmcn0 register = 0), the captured data becomes undefined. in addition, the intccn0 and in tccn1 interrupts do not occur (n = 0, 1). chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 216 (b) setting these registers as compare regi sters (cmsn0 and cmsn1 of tmcn1 = 1) when these registers are set as com pare registers, the tmn and register values are compared for each count clock, and an interrupt is generated by a match. if the cclrn bit of timer mode control register n1 (tmcn1) is set (1), the tmn value is cleared (0) at th e same time as a match with the ccn0 register (it is not cleared (0) by a match with the ccn1 register) (n = 0, 1). compare registers are equipped with a set/reset function . the corresponding timer output (ton) is set or reset, in synchronization with the genera tion of a match signal (n = 0, 1). the interrupt selection source differs accord ing to the function of the selected register. cautions 1. when writing to cap ture/compare register s n0 and n1, always set the tmcaen bit to 1 first. if the tmcaen bit is 0, the data that is written will be invalid. 2. write to capture/compare registers n0 and n1 after setting them as compare registers via tmcn0 and tmcn1 register settings. if they are set as capture registers (cmsn0 and cmsn1 bits of tmcn1 register = 0), no da ta is written even if a write operation is performed to ccn0 and ccn1. 3. when these registers are set as compare registers, intpn0 and intpn1 cannot be used (n = 0, 1). chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 217 7.4 control registers (1) timer mode control registers 00 and 10 (tmc00 and tmc10) the tmcn0 registers control the op eration of tmn (n = 0, 1). these registers can be read or written in 8-bit or 1-bit units. be sure to set bits 3 and 2 to 0. if they ar e set to 1, the operation is not guaranteed. these registers are cleared to 00h after reset. cautions 1. the tmcaen bit cannot be set at the same time as the other bits. the other bits and the registers of the other tmn units should always be set after the tmcaen bit has been set. also, to use external pins related to the ti mer function when the 16- bit timer/event counter is used, be sure to set (1) the tmcaen bit a fter setting the external pi ns to control mode. 2. when conflict occurs betw een an overflow and a tmcn0 register write, the ovfn bit value becomes the value written during the tmcn0 register write (n = 0, 1). (1/2) ovfn no overflow occurs overflow occurs ovfn 0 1 tmn register overflow detection tmcn0 (n = 0, 1) csn2 csn1 csn0 0 0 tmcen tmcaen 65432<1> after reset: 00h r/w address: tmc00 fffff606h tmc10 fffff616h when tmn has counted up from ffffh to 0000h, the ovfn bit becomes 1 and an overflow interrupt request (intovfn) is generated at the same time. however, if tmn is cleared to 0000h after a match at ffffh when the ccn0 register is set to compare mode (cmsn0 bit of tmcn1 register = 1) and clearing is enabled for a match when tmn and ccn0 are compared (cclrn bit of tmcn1 register = 1), then tmn is considered to be cleared and the ovfn bit does not become 1. also, no intovfn interrupt is generated. the ovfn bit retains the value 1 until 0 is written directly or until an asynchronous reset is performed because the tmcaen bit is 0. an interrupt operation due to an overflow is independent of the ovfn bit, and the interrupt request flag (ovfifn) for intovfn is not affected even if the ovfn bit is manipulated. if an overflow occurs while the ovfn bit is being read, the flag value changes, and the change is reflected when the next read operation occurs. <7> <0> chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 218 (2/2) the entire tmn unit is asynchronously reset. the supply of clocks to the tmn unit stops. clocks are supplied to the tmn unit. tmcaen 0 internal count clock control f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 csn2 0 0 0 0 1 1 1 1 internal count clock selection csn1 0 0 1 1 0 0 1 1 csn0 0 1 0 1 0 1 0 1 count disabled (stops at 0000h and does not operate). counting operation is performed. tmcen 0 1 tmn register operation control when tmcen = 0, the external pulse output (ton) becomes inactive (the active level of ton output is set by the alvn bit of the tmcn1 register). ? when the tmcaen bit is set to 0, the tmn unit can be asynchronously reset. ? when tmcaen = 0, the tmn unit is in a reset state. therefore, to operate tmn, the tmcaen bit must be set to 1. ? when the tmcaen bit is changed from 1 to 0, all registers of the tmn unit are initialized. when tmcaen is set to 1 again, the tmn unit registers must be set again. 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 219 (2) timer mode control registers 01 and 11 (tmc01 and tmc11) the tmcn1 registers control the op eration of tmn (n = 0, 1). these registers can be read or written in 8-bit units. these registers are set to 20h after reset. cautions 1. the various bits of the tmcn1 register must not be changed during timer operation. if they are to be changed, they must be changed after setting the tmcen bit of the tmcn0 register to 0. if these bits are overwr itten during timer operati on, operation cannot be guaranteed (n = 0, 1). 2. if the enton and alvn bits are changed at the same time, a glitch (spike shaped noise) may be generated in the ton pin output. either create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the enton and alvn bits do not change at the same time (n = 0, 1). 3. ton output is not changed by an external in terrupt signal (intpn0 or intpn1). to use the ton signal, specify that the capture/compare registers are compare registers (cmsn0 and cmsn1 bits of tmcn1 register = 1) (n = 0, 1). (1/2) ostn after the overflow, counting continues (free-running mode). after the overflow, the timer maintains the value 0000h, and counting stops (overflow stop mode). ostn 0 1 setting of operation when tmn register overflowed tmcn1 (n = 0, 1) enton alvn etin cclrn eclrn cmsn1 cmsn0 76 54 32 1 0 after reset: 20h r/w address: tmc01 fffff608h tmc11 fffff618h when ostn bit = 1, the tmcen bit of tmcn0 remains at 1. counting is restarted by writing 1 to the tmcen bit. external pulse output is disabled. external pulse output is enabled. enton 0 1 external pulse output (ton) enable/disable ? when ostn bit = 0, output of the alvn bit inactive level to the ton pin is fixed. the ton pin level is not changed even if a match signal from the corresponding compare register is generated. ? when ostn bit = 1, a compare register match causes ton output to change. however, if capture mode is set, ton output does not change. the alvn bit inactive level is output from the time when timer output is enabled until a match signal is first generated. ? if either ccn0 or ccn1 is specified as a capture register, the enton bit must be set to 0. chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 220 (2/2) clearing is disabled clearing is enabled (after the clearing, restarts counting) eclrn 0 1 tmn register clear enable/disable specification by external clear input (tclrn) the register operates as a capture register. the register operates as a compare register. cmsn1 0 1 capture/compare register (ccn1) operation mode selection the register operates as a capture register. the register operates as a compare register. cmsn0 0 1 capture/compare register (ccn0) operation mode selection clearing is disabled clearing is enabled (if ccn0 and tmn match during a compare operation, tmn is cleared) cclrn 0 1 tmn register clear enable/disable specification during compare operation low level high level alvn 0 1 external pulse output (ton) active level specification the initial value of the alvn bit is 1. specifies the input clock (internal). specifies the external clock (tin0). etin 0 1 count clock external/internal switch specification ? when etin bit = 0, the clock can be selected according to the csn2 to csn0 bits of tmcn0. ? when etin bit = 1, the valid edge can be selected according to the tesn1 and tesn0 bit specifications of sesn. remark a reset takes precedence for the flip -flop of the ton output (n = 0, 1). chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 221 (3) valid edge select registers 0 and 1 (ses0 and ses1) these registers specify the valid edge of an external in terrupt request (intp00, intp01, intp10, intp11, ti0, ti1, tclr10, and tclr11) from an external pin. the rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin. each of these registers can be r ead or written in 8-bit units. these registers are cleared to 00h after reset. caution the various bits of the sesn register must not be changed during ti mer operation. if they are to be changed, they must be changed after setting the tmcen bit of the tmcn0 register to 0. if the sesn register is overwri tten during timer operati on, operation cannot be guaranteed. falling edge rising edge setting prohibited both rising and falling edges tesn1 0 0 1 1 valid edge of tin pin tesn0 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges cesn1 0 0 1 1 valid edge of tclrn pin cesn0 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges iesn11 0 0 1 1 valid edge of intpn1 pin iesn10 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges iesn01 0 0 1 1 valid edge of intpn0 pin iesn00 0 1 0 1 tesn1 sesn (n = 0, 1) tesn0 cesn1 cesn0 iesn11 iesn10 iesn01 iesn00 76 54 32 1 0 after reset: 00h r/w address: ses0 fffff609h ses1 fffff619h chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 222 7.5 operation (1) count operation the 16-bit timer/event counter can function as a 16-bi t free-running timer or as an external signal event counter. the setting for the type of operation is specif ied by timer mode control registers n0 and n1 (tmcn0 and tmcn1) (n = 0, 1). when it operates as a free-running timer, if the ccn0 or ccn1 register and the tmn register count value match, an interrupt signal is generated and the timer output signal (ton) can be set or reset. also, a capture operation that holds the tmn register count val ue in the ccn0 or ccn1 register is performed, in synchronization with the valid edge that was detected from the external interrupt request input pin as an external trigger. the capture value is held until the next capture trigger is generated. caution when using the intpn0/tin0 pin as an external clock input pin (tin0), be sure to disable the intpn0 interrupt and set ccn0 to compare mode (n = 0, 1). figure 7-2. basic operation of 16-bit timer/event counter 0001h 0000h 0002h 0003h fbfeh fbffh 0001h 0002h 0000h tmn count clock ? count disabled tmcen 0 ? count start tmcen 1 ? count start tmcen 1 remark n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 223 (2) overflow when the tmn register has co unted the count clock from ffffh to 0000h, the ovfn bit of the tmcn0 register is set (1), and an overflow interrupt (intovfn) is generated at the same time (n = 0, 1). however, if the ccn0 register is set to compare mode (cmsn0 bit = 1) and to the value ffffh when ma tch clearing is enabled (cclrn bit = 1), then the tmn register is considered to be cleared and the ovfn bit is not set (1) when the tmn register changes from ffffh to 0000h. also, t he overflow interrupt (intovfn) is not generated . when the tmn register is changed from ffffh to 0000h because the tmcen bit chang es from 1 to 0, the tmn register is considered to be cleared, but the ovfn bit is not set (1) and no intovfn interrupt is generated. also, timer operation can be stopped after an overflow by setting the ostn bit of the tmcn1 register to 1. when the timer is stopped due to an overflow, the count operation is not restart ed until the tmcen bit of the tmcn0 register is set (1). operation is not affected ev en if the tmcen bit is set (1) during a count operation. remark n = 0, 1 figure 7-3. operation after overflow (when ostn = 1) overflow count start overflow ffffh ffffh tmn 0 intovfn ostn 1 tmcen 1 tmcen 1 remark n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 224 (3) capture operation the tmn register has two capture/compare registers. t hese are the ccn0 register and the ccn1 register. a capture operation or a compare oper ation is performed according to the settings of both the cmsn1 and cmsn0 bits of the tmcn1 register. if the cmsn1 and cm sn0 bits of the tmcn1 register are set to 0, the register operates as a capture register. a capture operation that captures and holds the tm n count value asynchronously to the count clock is performed in synchronization with an external trigger. the valid edge that is detected from an external interrupt request input pin (intpn0 or intpn1) is used as an external trigger (captur e trigger). the tmn count value during counting is captured and held in the captur e register, in synchronization with that capture trigger signal. the capture register value is hel d until the next capture trigger is generated. also, an interrupt request (intccn0 or intccn1) is generated by intpn0 or intpn1 signal input. the valid edge of the capture trigger is se t by valid edge select register n (sesn). if both the rising and falling edges are set as capture trig gers, the input pulse width from an external source can be measured. also, if only one of the edges is set as the capture trigger, the input pulse cycle can be measured. remark n = 0, 1 figure 7-4. capture operation example (tm1) tm1 0 tmce1 intp11 cc11 (capture register) n n (capture trigger) (capture trigger) remarks 1. when the tmce1 bit is 0, no capture operat ion is performed even if intp11 is input. 2. valid edge of intp11: rising edge chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 225 figure 7-5. tm1 capture operation e xample (when both edges are specified) tm1 ? count start tmce1 1 ? overflow ovf1 1 d0 d1 d2 d0 d1 d2 interrupt request (intp11) (tm1 count values) capture register (cc11) remark d0 to d2: tm1 register count values chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 226 (4) compare operation the tmn register has two capture/compare registers. t hese are the ccn0 register and the ccn1 register. a capture operation or a compare oper ation is performed according to the settings of both the cmsn1 and cmsn0 bits of the tmcn1 register. if the cmsn1 and cm sn0 bits of the tmcn1 register are set to 1, the register operates as a compare register. a compare operation that compares t he value that was set in the compare register and the tmn register count value is performed. if the tmn register count value matches the value of the compare register, which had been set in advance, a match signal is sent to the output controller. the ma tch signal causes the timer output pin (ton) to change and an interrupt request signal (intccnn) to be generated at the same time. if the ccn0 or ccn1 registers are set to 0000h, the 0000 h after the tmn register counts up from ffffh to 0000h is judged as a match. in this case, the tmn register value is cleared (0) at the next count timing, however, this 0000h is not judged as a match. also, the 0000h when the tmn register begins counting is not judged as a match. if match clearing is enabled (cclrn bit = 1) for the ccn0 register, the tmn register is cleared when a match with the tmn register occurs during a compare operation. remark n = 0, 1 figure 7-6. compare operation example (whe n cclr1 = 1 and cc10 is other than 0000h) 0001h 0000h n n n ? 1 tm1 compare register (cc10) match detection (intcc10) remarks 1. a match is detected immediately after the count-up, and the match detection signal is generated. 2. n 0000h chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 227 figure 7-7. compare operation exam ple (when cclr1 = 1 and cc10 is 0000h) 0001h 0000h 0000h 0000h ffffh tm1 intovf1 count-up compare register (cc10) match detection (intcc10) remark a match is detected immediately after the count-up, and the match detection signal is generated. chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 228 (5) external pulse output the 16-bit timer/event counter has two timer output pins (ton). an external pulse output (ton) is generated when a ma tch of the two compare registers (ccn0 and ccn1) and the tmn register is detected. if a match is detected when the tmn r egister count value and the ccn0 val ue are compared, the output level of the ton pin is set. also, if a match is detected wh en the tmn register count value and the ccn1 value are compared, the output level of the ton pin is reset. the output level of the to n pin can be specified by the tmcn1 register. remark n = 0, 1 table 7-2. ton output control ton output etin alvn external pulse output output level 0 0 disable high level 0 1 disable low level 1 0 enable when the ccn0 register is matched: low level when the ccn1 register is matched: high level 1 1 enable when the ccn0 register is matched: high level when the ccn1 register is matched: low level remark n = 0, 1 figure 7-8. tm1 compare operation example (set/reset output mode) tm1 register count value 0 ffffh ? count start tmce1 1 ? overflow ovf1 1 ? overflow ovf1 1 cc11 cc10 ffffh cc11 cc10 cc10 interrupt request (intcc10) interrupt request (intcc11) to1 pin ento1 1 alv1 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 229 7.6 application examples (1) interval timer by setting the tmcn0 and tmcn1 registers as shown in fi gure 7-9, the 16-bit timer/ event counter operates as an interval timer that repeatedly generates interrupt requests with the value that was preset in the ccn0 register as the interval. when the counter value of the tmn register matches the setting value of the ccn0 register, the tmn register is cleared (0000h) and an interrupt request signal (intccn0) is generated at the same time that the count operation resumes. remark n = 0, 1 figure 7-9. contents of register settings when 16- bit timer/event counter is used as interval timer supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 1 0 0/1 1 ostn enton alvn etin cclrn cmsn1 cmsn0 0/1 0/1 0/1 0/1 0 0 1 1 ovfn tmcn0 tmcn1 csn2 csn1 csn0 tmcen tmcaen use ccn0 register as compare register clear tmn register due to match with ccn0 register continue counting after tmn register overflows eclrn remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 230 figure 7-10. interval time r operation timing example 0000h 0001h p 0000h 0001h pp p p p p 0000h 0001h t count start interval time interval time interval time count clock tmn register ccn0 register intccn0 interrupt clear clear remarks 1. p: setting value of ccn0 register (0000h to ffffh) t: count clock cycle interval time = (p + 1) t 2. n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 231 (2) pwm output by setting the tmcn0 and tmcn1 registers as shown in figure 7-11, the 16-bit time r/event counter can output a pwm signal, whose frequency is determined according to the setting of the csn2 to csn0 bits of the tmcn0 register, with the values that were preset in the ccn0 and ccn1 registers determining the intervals. when the counter value of the tmn register matches th e setting value of the ccn0 register, the ton output becomes active. then, when the counter value of t he tmn register matches t he setting value of the ccn1 register, the ton output becomes inactive. the tmn regist er continues counting. when it overflows, its count value is cleared to 0000h, and the register continues co unting. in this way, a pwm signal whose frequency is determined according to the setting of the csn2 to csn0 bits of the tmcn0 register can be output. when the setting value of the ccn0 register and the setting value of the ccn1 register are the same, the ton output remains inactive and does not change. the active level of the ton output can be set by the alvn bit of the tmcn1 register. remark n = 0, 1 figure 7-11. contents of register settings when 16-bit timer/event counter is used for pwm output supply input clocks to internal units enable count operation 0 1 0/1 0/1 0 0/1 1 1 ostn enton alvn etin cclrn cmsn1 cmsn0 0/1 0/1 0/1 0/1 0 0 1 1 ovfn tmcn0 tmcn1 csn2 csn1 csn0 tmcen tmcaen use ccn0 register as compare register use ccn1 register as compare register disable clearing of tmn register due to match with ccn0 register enable external pulse output (ton) continue counting after tmn register overflows eclrn remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 232 figure 7-12. pwm output timing example 0000h 0001h p ppp p p qqq q q qpq 0000h ffffh 0001h count clock tmn register ccn0 register ccn1 register intccn0 interrupt intccn1 interrupt ton (output) count start clear t remarks 1. p: setting value of ccn0 register (0000h to ffffh) q: setting value of cc n1 register (0000h to ffffh) p q t: count clock cycle pwm cycle = 65,536 t 65,536 p q duty ? = 2. in this example, the active level of the ton output is set to the high level. 3. n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 233 (3) one-shot pulse output by setting the tmcn0 and tmcn1 registers as shown in figure 7-13, the 16-bit timer/event counter can output a one-shot pulse from the ton pin by using the valid edge of the tclrn pin as an external trigger. the valid edge of the tclrn pin is selected according to the cesn0 and cesn1 bits of the sesn register. the rising edge, falling edge, or both rising and falling edges can be selected as the valid edge of both pins. the tmn register is cleared and started by setting a valid edge to the tclrn pin. ton output becomes active at the count value set in advance to the ccn0 register. after that, the ton output becomes inactive at the count value set in advance to ccn1 register. the active le vel of the ton output can be set by the alvn bit of the tmcn1 register. when the setting value of the ccn0 register and the setting value of the ccn1 register are the same, the ton output remains inactive and does not change. the active level of the ton output can be se t by the alvn bit of the tmcn1 register. remark n = 0, 1 figure 7-13. contents of register settings when 16-bit timer/event counter is used for one-shot pulse output supply input clocks to internal units enable count operation 1 1 0/1 0/1 0 1 1 1 ostn enton alv n etin cclrn eclrn cmsn1 cmsn0 0/1 0/1 0/1 0/1 0 0 1 1 ovfn tmcn0 tmcn1 csn2 csn1 csn0 tm cen tm caen use ccn0 register as compare register use ccn1 register as compare register disable clearing of tmn reigster due to match with ccn0 register enable external pulse output (ton) enable clearing of tmn register by tclrn input timer holds 0000h and stops counting after tmn register overflows remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 234 figure 7-14. one-shot pulse ou tput operation timing example 0000h 0001h p ppp p qqq q q 0000h ffffh count start count stop count clock tmn register ccn0 register ccn1 register intccn0 interrupt intccn1 interrupt ton (output) t remarks 1. p: setting value of cc n0 register (0000h to ffffh) q: setting value of cc n1 register (0000h to ffffh) p q t: count clock cycle 2. in this example, the valid edge of the tclrn input is set to the rising edge and the active level of the ton output is set to the high level. 3. n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 235 (4) cycle measurement by setting the tmcn0 and tmcn1 registers as shown in figure 7-15, the 16-bit timer/event counter can measure the cycle of signals input to the intpn0 or intpn1 pin. the valid edge of the intpn0 pin is selected accordi ng to the iesn01 and iesn00 bi ts of the sesn register, and the valid edge of the intpn1 pin is selected accordi ng to the iesn11 and iesn10 bits of the sesn register. either the rising edge, the falling edge, or both edges can be selected as the valid edges of both pins. if the ccn0 register is set as a captur e register, the valid edge input of the intpn0 pin is set as the trigger for capturing the tmn register value in t he ccn0 register. when this value is captured, an intccn0 interrupt is generated. similarly, if the ccn1 register is se t as a capture register, the valid edge input of the intpn1 pin is set as the trigger for capturing the tmn register value in the ccn1 register. when this value is captured, an intccn1 interrupt is generated. the cycle of signals input to the intpn0 pin is calculated by obtaining the difference between the tmn register?s count value (dx) that was captured in the ccn 0 register according to the x-th valid edge input of the intpn0 pin and the tmn register?s count value (d(x+1)) th at was captured in the ccn0 register according to the (x+1)-th valid edge input of the intpn0 pin and multiplying the val ue of this difference by the cycle of the internal count clock. the cycle of signals input to the intpn1 pin is calculated by obtaining the difference between the tmn register?s count value (dx) that was captured in the ccn 1 register according to the x-th valid edge input of the intpn1 pin and the tmn register?s count value (d(x+1)) th at was captured in the ccn1 register according to the (x+1)-th valid edge input of the intpn1 pin and multiplying the val ue of this difference by the cycle of the internal count clock. remark n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 236 figure 7-15. contents of register settings when 16-bi t timer/event counter is used for cycle measurement supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 0/1 0/1 0 0 ostn enton alvn etin cclrn cmsn1 cmsn0 0/1 0/1 0/1 0/1 0 0 1 1 ovfn tmcn0 tmcn1 csn2 csn1 csn0 tmcen tmcaen use ccn0 register as capture register (when measuring the cycle of intpn0 input) use ccn1 register as capture register (when measuring the cycle of intpn1 input) continue counting after tmn register overflows eclrn remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 237 figure 7-16. cycle measurement operation timing example 0001h 0000h 0001h 0000h ffffh d0 d1 d2 d3 d3 d2 d1 d0 (d1 ? d0) t (d3 ? d2) t {(10000h ? d1) + d2} t note t count clock tmn register intpn0 (input) ccn0 register intccn0 interrupt intovfn interrupt no overflow overflow occurs no overflow clear count start note when an overflow occurs once. remarks 1. d0 to d3: tmn register count values t: count clock cycle 2. in this example, the valid edge of the intpn0 i nput has been set to both edges (rising and falling). 3. n = 0, 1 chapter 7 16-bit timer/event counters 0 and 1 user?s manual u15905ej2v1ud 238 7.7 cautions various cautions concerning the 16-bit timer/event counter are shown below. (1) if a conflict occurs between the reading of the ccn0 register and a capture operat ion when the ccn0 register is used in capture mode, an external trigger (intpn0) valid edge is detected and an external interrupt request signal (intccn0) is generated, however, the ti mer value is not stored in the ccn0 register. (2) if a conflict occurs between the reading of the ccn1 register and a capture operat ion when the ccn1 register is used in capture mode, an external trigger (intpn1) valid edge is detected and an external interrupt request signal (intccn1) is generated, however, the ti mer value is not stored in the ccn1 register. (3) the following bits and registers must not be rewritten during operation (tmcen = 1). ? csn2 to csn0 bits of tmcn0 register ? tmcn1 register ? sesn register (4) the tmcaen bit of the tmcn0 register is a tmn rese t signal. to use tmn, first set (1) the tmcaen bit. (5) the analog noise elimination time + two cycles of the input clock are required to detect the valid edge of the external interrupt request signal (intpn0 or intpn1) or the external clock input (tin). therefore, edge detection will not be performed normally for changes that are less than the analog noise elimination time + two cycles of the input clock. only two clocks of f xx are required for detection of t he internal clear input (tclr1n) valid edge. (6) the operation of an external interrupt request sign al (intccn0 or intccn1) is automatically determined according to the operating state of the capture/compare register. when the captur e/compare register is used for a capture operation, the external interrupt request signal is used for valid edge detection. when the capture/compare register is used for a compare operatio n, the external interrupt request signal is used for an interrupt indicating a match with the tmn register. (7) if the enton and alvn bits are changed at the same ti me, a glitch (spike shaped noise) may be generated in the ton pin output. either create a ci rcuit configuration that will not malfunct ion even if a glitch is generated or make sure that the enton and alvn bits are not changed at the same time. remark n = 0, 1 user?s manual u15905ej2v1ud 239 chapter 8 8-bit timer/ event counters 2 to 5 8.1 functional overview 8-bit timer/event counter n has the following two modes (n = 2 to 5). ? mode using 8-bit timer/event counter alone (individual mode) ? mode using cascade connection (16-bit resolution: cascade connection mode) these two modes are described below. (1) mode using 8-bit timer/event counter alone (individual mode) 8-bit timer/event counter n operates as an 8-bit timer/event counter. the following functions can be used. ? interval timer ? external event counter ? square wave output ? pwm output (2) mode using cascade connection (16-bi t resolution: cascade connection mode) tm2 and tm3, and tm4 and tm5 can be used as 16-bit timer/event counters when they are connected in cascade. the following functions can be used. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square wave output with 16-bit resolution the block diagram of 8-bit timer/event counter n is shown next. chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 240 figure 8-1. block diagram of 8-bit timer/event counter n match clear ovf tin count clock note 1 selector internal bus internal bus 3 tcln2 tcln1 tcln0 tmcen tmcn6 tmcm4 lvsn lvrn tmcn1 toen 8-bit timer mode control register n (tmcn) 8-bit timer compare register n (crn) 8-bit timer counter n (tmn) ton inttmn selector invert level s r q inv s r q mask circuit timer clock selection register n (tcln) selector selector note 2 notes 1. the count clock is set by the tcln register. 2. serial interface clock (tm4, tm5 only) remarks 1. ? ? are signals that can be directly connected to ports. 2. n = 2 to 5, m = 3, 5 8.2 configuration 8-bit timer/event counter n consists of the following hardware (n = 2 to 5). table 8-1. configuration of 8-bit timer/event counter n item configuration timer registers 8-bit timer counters 2 to 5 (tm2 to tm5) 16-bit timer counters 23 and 45 (tm23, tm 45): only when using cascade connection registers 8-bit timer compare registers 2 to 5 (cr2 to cr5) 16-bit timer compare registers 23 and 45 (cr23, cr45): only when using cascade connection timer output to2 to to5 control registers note timer clock selection register s 2 to 5 (tcl2 to tcl5) timer clock selection registers 23 and 45 (tcl23, tcl45): only when using cascade connection 8-bit timer mode control registers 2 to 5 (tmc2 to tmc5) 16-bit timer mode control registers 23 and 45 (tmc23, tmc45): only when using cascade connection note when using the functions of the tin and ton pins, refer to table 4-18 using alternate function of port pins . chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 241 (1) 8-bit timer counters 2 to 5 (tm2 to tm5) the tmn register is an 8-bit read-only re gister that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. tm2 and tm3, and tm4 and tm5 can be used as 16-bit timers when they are connected in cascade. when these timers are used as 16-bit timers, their values can be read by using a 16-bit memory manipulation instruction. however, because these registers are con nected by an internal 8-bit bus, the tmm register and tmm+1 register must be read divided into two times. therefore, read these regi sters twice and compare the values, taking into consideration that the reading occurs during a count change. in the following cases, the count value becomes 00h. ? after reset ? when the tmcen bit of 8-bit timer mode control register n (tmcn) is cleared ? tmn register and crn register match in the mode in which clear & start occurs on a match between the tmn register and 8-bit timer compare register n (crn) caution when connected in cascade, these registers become 00h even when the tcem bit in the lowest timer (tmm) is cleared. remark n = 2 to 5 m = 2, 4 (2) 8-bit timer compare regist ers 2 to 5 (cr2 to cr5) the crn register can be read and written in 8-bit units. in a mode other than the pwm mode, the value set to the crn register is always compared to the count value of 8-bit counter n (tmn), and if the two values match, an interrupt reques t signal (inttmn) is generated. in the pwm mode, tmn register overflow causes the to n pin output to change to the active level, and when the values of the tmn regist er and the crn register match, the ton pin output changes to the inactive level. the value of the crn register can be set in the range of 00h to ffh. when tm2 and tm3, and tm4 and tm5 are connected in cascade as 16-bit timers, the crm register and crm+1 register function as 16-bit timer compare re gisters 23 and 45 (cr23 and cr45). the counter value and register value are compared in 16-bit lengths, a nd if they match, an interrupt request (inttmm) is generated. cautions 1. in the mode in wh ich clear & start occurs upon a matc h of the tmn register and crn register (tmcn6 =0), do not write a differen t value to the crn register during the count operation. 2. in the pwm mode, set the crn register re write interval to three or more count clocks (clock selected with timer clock selection register n (tcln)). 3. before changing the value of the crn regi ster when using a cascade connection, be sure to stop the timer operation. remark n = 2 to 5 m = 2, 4 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 242 8.3 control registers the following two registers are used to co ntrol 8-bit timer/event counter n. ? timer clock selection register n (tcln) ? 8-bit timer mode control register n (tmcn) remark to use the functions of the tin and ton pins, refer to table 4-18 using alternate function of port pins . (1) timer clock selection regist ers 2 to 5 (tcl2 to tcl5) these registers set the count clock of 8-bit timer/event counter n and the valid edge of the tin pin input. the tcln register can be read or written in 8-bit units. these registers are cleared to 00h after reset. (a) timer clock selection registers 2 and 3 (tcl2 and tcl3) falling edge of tin rising edge of tin f xx /4 f xx /8 f xx /16 f xx /32 f xx /128 f xx /512 count clock selection tcln2 0 0 0 0 1 1 1 1 tcln1 0 0 1 1 0 0 1 1 tcln0 0 1 0 1 0 1 0 1 20 mhz 10 mhz ? ? 200 ns 400 ns 800 ns 1.6 s 6.4 s 25.6 s ? ? 400 ns 800 ns 1.6 s 3.2 s 12.8 s 51.2 s clock f xx 0 tcln (n = 2, 3) 0 0 0 0 tcln2 tcln1 tcln0 after reset: 00h r/w address: tcl2 fffff644h, tcl3 fffff645h 76 54 32 1 0 ? cautions 1. before overwriting the tcln register with different data, stop the timer operation. 2. ti2 and ti3 are used altern ately as p01/intp0 and p02/intp2, respectively, so when using the tin pin function, set the pmc01 or pmc02 bit of the pmc0 register to 1 before starting timer operation. edge detection may not be co rrectly performed if the bit is manipulated after the timer starts operating. remark when tcl2 and tcl3 are connected in cascade, the tcl3 register settings are invalid. chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 243 (b) timer clock selection registers 4 and 5 (tcl4 and tcl5) falling edge of tin rising edge of tin f xx /4 f xx /8 f xx /16 f xx /32 f xx /128 f xx /256 count clock selection tcln2 0 0 0 0 1 1 1 1 tcln1 0 0 1 1 0 0 1 1 tcln0 0 1 0 1 0 1 0 1 20 mhz 10 mhz ? ? 200 ns 400 ns 800 ns 1.6 s 6.4 s 12.8 s ? ? 400 ns 800 ns 1.6 s 3.2 s 12.8 s 25.6 s clock f xx 0 tcln (n = 4, 5) 0 0 0 0 tcln2 tcln1 tcln0 after reset: 00h r/w address: tcl4 fffff654h, tcl5 fffff655h 76 54 32 1 0 cautions 1. before overwriting the tcln register with different data, stop the timer operation. 2. ti4 and ti5 are used altern ately as p03/intp3 and p04/intp4, respectively, so when using the tin pin function, set the pmc03 or pmc04 bit of the pmc0 register to 1 before starting timer operation. edge detection may not be co rrectly performed if the bit is manipulated after the timer starts operating. remark when tcl4 and tcl5 are connected in cascade, the tcl5 register settings are invalid. chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 244 (2) 8-bit timer mode control registers 2 to 5 (tmc2 to tmc5) the tmcn register performs the following six settings. ? controls counting by 8-bit timer counters 2 to 5 (tm2 totm5) ? selects the operation mode of the tmn register ? selects the individual mode or cascade connection mode ? sets the status of t he timer output flip-flop ? controls the timer output flip-flop or selects t he active level in the pwm (free-running) mode ? controls timer output the tmcn register can be read or written in 8-bit or 1-bit units. these registers are cleared to 00h after reset. remark n = 2 to 5 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 245 tmcen counting is disabled after the counter is cleared to 0 (counter disabled) start count operation tmcen 0 1 control of count operation of 8-bit timer/event counter n tmcn (n = 2 to 5, m = 3, 5) tmcn6 0 tmcm4 note lvsn lvrn tmcn1 toen mode in which clear & start occurs on match between tmn register and crn register pwm (free-running) mode tmcn6 0 1 selection of operation mode of 8-bit timer/event counter n individual mode cascade connection mode (connected with tm2 or tm4) tmcm4 0 1 selection of individual mode or cascade connection mode unchanged reset timer output f/f to 0 set timer output f/f to 1 setting prohibited lvsn 0 0 1 1 setting of status of timer output f/f lvrn 0 1 0 1 after reset: 00h r/w address: tmc3 fffff646h tmc3 fffff647h disable inversion operation enable inversion operation high active low active tmcn1 0 1 other than pwm (free-running) mode (tmcn6 = 0) controls timer f/f pwm (free-running) mode (tmcn6 = 1) selects active level disable output (ton pin is low level) enable output toen 0 1 timer output control <7>6543210 tmc4 fffff656h tmc5 fffff657h note bit 4 of the tmc2 and tmc4 registers is fixed to 0. cautions 1. the lvsn and lvrn bit settings ar e valid in modes other than the pwm mode. 2. do not rewrite the tmcn1 bit and toen bit at the same time. 3. when switching to the pwm mode, do not rewrite the tmcn6 bit and the lvsn and lvrn bits at the same time. 4. before rewriting the tmcn6 bit or tmcm4 bit, stop the timer operation. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tmcen = 0. 2. when the lvsn and lvrn bits are read, 0 is read. 3. the values of the tmcn6, lvsn, lvrn, tmcn1, and toen bits are reflected to the ton output regardless of the tmcen value. chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 246 8.4 operation 8.4.1 operation as interval timer (8 bits) 8-bit timer/event counter n operates as an interval timer th at repeatedly generates interr upts at the interval of the count value preset in 8-bit timer compare register n (crn). if the count value in 8-bit timer counter n (tmn) matches the value set in the crn register, the value of the tmn register is cleared to 0 and counting is continued, and at the same time, an interrupt request signal (inttmn) is generated. setting method <1> set each register. ? tcln register: selects the count clock (t). ? crn register: compare value (n) ? tmcn register: stops count operat ion and selects the mode in which clear & start occurs on a match between the tmn register and crn re gister (tmcn register = 0000xxx0b, : don?t care). <2> when the tmcen bit of the tmcn register is set to 1, the count operation starts. <3> when the values of the tmn regi ster and crn register match, inttm n is generated (tmn register is cleared to 00h). <4> then, inttmn is repeatedly generated at the same interval. to stop counting, set tmcen = 0. interval time = (n + 1) t: n = 00h to ffh caution during interval timer operation, do not rewrite the value of the crn register. figure 8-2. timing of interval timer operation (1/2) basic operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tmn count value crn tmcen inttmn count start remark n = 2 to 5 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 247 figure 8-2. timing of interval timer operation (2/2) when crn register = 00h t interval time 00h 00h 00h 00h 00h count clock tmn count value crn tmcen inttmn remark n = 2 to 5 when crn register = ffh t 01h 00h feh ffh 00h feh ffh 00h ffh ffh ffh count clock tmn count value crn tmcen inttmn ton interval time interrupt acknowledgment interrupt acknowledgment remark n = 2 to 5 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 248 8.4.2 operation as external event counter (8 bits) the external event counter count s the number of clock pulses input to the tin pin from an external source by using 8-bit timer counter n (tmn). each time the valid edge specified by timer clock selecti on register n (tcln) is input to the tin pin, the tmn register is incremented. either the rising edge or the falling edge can be specified as the valid edge. when the count value of the tmn register matches the va lue of 8-bit timer compare register n (crn), the tmn register is cleared to 0 and an interrupt request signal (inttmn) is generated. setting method <1> set each register. ? tcln register: selects the tin input edge. falling edge of tin pin tlcn = 00h rising edge of tin pin tcln = 01h ? crn register: compare value (n) ? tmcn register: stops count operation, selects t he mode in which clear & start occurs on a match between the tmn register and crn register, disables timer output f/f inversion operation, and disables timer output. (tmcn register = 0000xx00b, : don?t care) <2> when the tmcen bit of the tmcn register is set to 1, the counter counts the num ber of pulses input from tin. <3> when the values of the tmn regi ster and crn register match, inttm n is generated (tmn register is cleared to 00h). <4> then, inttmn is generated each time the values of the tmn register and crn register match. inttmn is generated when the valid edge of tin is input n + 1 times: n = 00 to ffh caution during external event counter operation, do not rewrite the value of the crn register. remark n = 2 to 5 figure 8-3. timing of external event coun ter operation (with ri sing edge specified) 00h 01h 02h 03h 04h 05h n e 1 n n 00h 01h 02h 03h tin crn inttmn tmcen tmn count value count start remark n = 2 to 5 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 249 8.4.3 square-wave output oper ation (8-bit resolution) a square wave with any frequency can be output at an interval specified by the value preset in 8-bit timer compare register n (crn). by setting the toen bit of 8-bit timer mode control register n (tmcn) to 1, the output status of the ton pin is inverted at an interval specified by the count value preset in the crn register. in this way, a square wave of any frequency can be output (duty = 50%) (n = 2 to 5). setting method <1> set each register. ? tcln register: selects the count clock (t). ? crn register: compare value (n) ? tmcn register: stops count operation, selects t he mode in which clear & start occurs on a match between the tmn register and crn register. lvsn lvrn timer output f/f status setting 1 0 high-level output 0 1 low-level output enables timer output f/f inversion o peration, and enables timer output. (tmcn register = 00001011b or 00000111b) <2> when the tmcen bit of the tmcn regi ster is set to 1, counting starts. <3> when the values of the tmn regi ster and crn register match, the timer output f/f is inverted. moreover, inttmn is generated and the tm n register is cleared to 00h. <4> then, the timer f/f is inverted during the same inte rval and a square wave is output from the ton pin. frequency = 1/2t (n + 1): n = 00h to ffh caution do not rewrite the value of the crn register during square-wave output. chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 250 figure 8-4. timing of square-wave output operation 00h 01h 02h n ? 1 n 01h 02h n n 00h count clock crn ton tmn count value inttmn tmcen count start 00h n ? 1 t note the initial value of the ton output can be set using the lvsn and lvrn bits of the tmcn register. remark n = 0, 1 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 251 8.4.4 8-bit pwm output operation by setting the tmcn6 bit of 8-bit timer mode control regist er n (tmcn) to 1, 8-bit timer/event counter n performs pwm output. pulses with the duty factor determined by the value set in 8-bit timer compare register n (crn) are output from the ton pin. set the width of the active level of the pwm pulse in the crn register. the active level can be selected using the tmcn1 bit of the tmcn register. the count clock can be selected using time r clock selection register n (tcln). pwm output can be enabled/disabled by the toen bit of the tmcn register. caution the crn register rewrite interval must be three or more operation clocks (set by the tcln register). (1) basic operation of pwm output setting method <1> set each register. ? tcln register: selects the count clock (t). ? crn register: compare value (n) ? tmcn register: stops count operation, select s pwm mode, and leave timer output f/f unchanged. tmcn1 active level selection 0 active high 1 active low timer output enabled (tmcn register = 01000001b or 01000011b) <2> when the tmcen bit of the tmcn regist er is set to 1, counting starts. pwm output operation <1> when counting starts, pwm output (output from t he ton pin) outputs the inactive level until an overflow occurs. <2> when an overflow occurs, the active level set by setting method <1> is output. the active level is output until the value of the crn r egister and the count value of 8-bi t timer counter n (tmn) match. <3> when the value of the crn register and the count value match, the inactive level is output and continues to be output until an overflow occurs again. <4> then, steps <2> and <3> are repeat ed until counting is stopped. <5> when counting is stopped by setting tmcen to 0, pwm output becomes inactive. cycle = 2 8 t, active level width = nt, duty = n/2 8 : n = 00 to ffh remark n = 2 to 5 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 252 (a) basic operation of pwm output figure 8-5. timing of pwm output operation basic operation (active level = h) 00h n + 1 n n 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h active level inactive level active level count clock tmn count value crn tmcen inttmn ton when crn register = 00h 00h n + 1 n + 2 n 00h 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level count clock tmn count value crn tmcen inttmn ton when crn register = ffh 00h n + 1 n + 2 n ffh 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level inactive level active level active level count clock tmn count value crn tmcen inttmn ton remark n = 2 to 5 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 253 (b) operation based on crn register transitions figure 8-6. timing of operation b ased on crn register transitions when the value of the crn register changes from n to m before the rising edge of the ffh clock the value of the crn register is reloaded at the overflow that occurs immediately after. n n + 1 n + 2 m n <1> crn transition (n m) m m + 1 m + 2 m m +1m + 2 ffh 02h 00h 01h ffh 02h 00h 01h count clock tmn count value crn tmcen h inttmn ton <2> when the value of the crn register changes from n to m after the rising edge of the ffh clock the value of the crn register is reloaded at the second overflow. n n + 1 n + 2 n nn <1> crn transition (n m) m n + 1 n + 2 m m + 1 m + 2 ffh 03h 02h 00h 01h ffh 02h 00h 01h count clock tmn count value crn tmcen h inttmn ton <2> caution in the case of reload from the crn register between <1> and <2>, the value that is actually used differs (read value: m; actu al value of crn register: n). remark n = 2 to 5 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 254 8.4.5 operation as interv al timer (16 bits) the v850es/sa2 and v850es/sa3 are provided with a 16- bit register that can be used only during cascade connection. the 16-bit resolution timer/event counter mode is select ed by setting the tmc34 and tmc54 bits of 8-bit timer mode control registers 3 and 5 (tmc3 and tmc5) to 1. 8-bit timer/event counter n operates as an interval time r by repeatedly generating interrupts using the count value preset in 16-bit timer compare registers 23 and 45 (cr23 and cr45) as the interval. in the following description, tm2 and tm3 are used. read tm2 and tm3 as tm4 and tm5 when using tm4 and tm5. setting method (when tm2 and tm3 are connected in cascade) <1> set each register. ? tcl2 register: selects the count clock (t) (the tcl3 register does not need to be set in cascade connection) ? cr2 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr3 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc2, tmc3 register: selects the mode in whic h clear & start occurs on a match between tm23 register and cr23 register ( : don?t care) tmc2 register = 0000xx00b tmc3 register = 0001xx00b <2> set the tmce3 bit of the tmc3 register to 1. then set the tmce2 bit of the tmc2 register to 1 to start the count operation. <3> when the values of the tm23 register and cr23 register connected in cascade match, inttm2 is generated (the tm23 register is cleared to 0000h). <4> inttm2 is then generated repeatedly at the same interval. interval time = (n + 1) t: n = 0000h to ffffh cautions 1. to write using 8-bit access during cascade connection, set th e tmce3 bit to 1 at operation start and then set the tmce2 bit to 1. when operation is stopped, set the tmce2 bit to 0 and then set the tmce3 bit to 0. 2. during cascade connection, ti2 input, to 2 output, and inttm2 input are used while ti3 input, to3 output, and inttm3 input are not, so set bits lvs3, lvr3, tmc31, and toe3 to 0. 3. do not change the value of the cr23 register during timer operation. chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 255 figure 8-7 shows a timing example of the cascade connection mode with 16-bit resolution. figure 8-7. cascade connection mode with 16-bi t resolution (when tm2 and tm3 are connected) 00h n + 1 01h 00h ffh 00h 01h ffh 00h ffh m ? 1 01h 00h 00h na 01h 00h 02h m 00h 00h b n n m interval time operation ebabled, count start interrupt occurrence, level inverted, counter cleared operation stopped count clock tm2 count value tm3 count value tmce3 inttm2 cr3 tmce2 cr2 chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 256 8.4.6 operation as external event counter (16 bits) the v850es/sa2 and v850es/sa3 are provided with a 16- bit register that can be used only during cascade connection. the 16-bit resolution timer/event counter mode is select ed by setting the tmc34 and tmc54 bits of 8-bit timer mode control registers 3 and 5 (tmc3 and tmc5) to 1. the external event counter counts the number of clock pulses input to the ti2 and ti4 pins from an external source using 16-bit timer counters 23 and 45 (tm23 and tm45). in the following description, tm2 and tm3 are used. read tm2 and tm3 as tm4 and tm5 when using tm4 and tm5. setting method (when tm2 and tm3 are connected in cascade) <1> set each register. ? tcl2 register: selects the ti2 input edge. (the tcl3 register does not have to be set during cascade connection.) falling edge of ti2 tcl2 = 00h rising edge of ti2 tcl2 = 01h ? cr2 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr3 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc2, tmc3 registers: stops count operation, selects the clear & stop mode entered on a match between the tm23 register and cr23 regi ster, disables timer output f/f inversion, and disables timer output. ( : don?t care) tmc2 register = 0000xx00b tmc3 register = 0001xx00b <2> set the tmce3 bit of the tmc3 register to 1. then set the tmce2 bit of the tmc2 register to 1 and count the number of pulses input from ti2. <3> when the values of the tm23 register and cr23 register connected in cascade match, inttm2 is generated (the tm23 register is cleared to 0000h). <4> inttm2 is then generated each time the values of the tm23 register and cr23 register match. inttm2 is generated when the valid edge of ti2 is input n + 1 times: n = 0000 to ffffh cautions 1. during external even t counter operation, do not rewrite the value of the crn register. 2. to write using 8-bit access during cascade connection, set the tmce3 bit to 1 and then set the tmce2 bit to 1. when operation is stopped, set the tmce2 bit to 0 and then set the tmce3 bit to 0. 3. during cascade connection, ti2 input and inttm2 input are used while ti3 input, to3 output, and inttm3 input are not, so set bits lvs3, lvr3, tmc31, and toe3 to 0. 4. do not change the value of the cr23 re gister during external counter operation. chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 257 8.4.7 square-wave output operat ion (16-bit resolution) the v850es/sa2 and v850es/sa3 are provided with a 16- bit register that can be used only during cascade connection. the 16-bit resolution timer/event counter mode is select ed by setting the tmc34 and tcm54 bits of 8-bit timer mode control registers 3 and 5 (tmc3 and tmc5) to 1. 8-bit timer/event counter n outputs a square wave of an y frequency using the interval preset in 16-bit timer compare registers 23 and 45 (cr23 and cr45). in the following description, tm2 and tm3 are used. read tm2 and tm3 as tm4 and tm5 when using tm4 and tm5. setting method (when tm2 and tm3 are connected in cascade) <1> set each register. ? tcl2 register: tcl2 selects the count clock (t) (the tcl3 register does not have to be set in cascade connection) ? cr2 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr3 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc2, tcm3 registers: stops count operation, sele cts the mode in which clear & start occurs on a match between the tm23 r egister and cr23 register. lvs2 lvr2 timer output f/f status settings 1 0 high-level output 0 1 low-level output enables timer output f/f inversion, and enables timer output. tmc2 register = 00001011b or 00000111b tmc3 register = 00010000b <2> set the tmce3 bit of the tmc3 register to 1. then set the tmce2 bit of the tmc2 register to 1 to start the count operation. <3> when the values of the tm23 regi ster and the cr23 register connected in cascade match, the to2 timer output f/f is inverted. moreover, inttm2 is generat ed and the tm23 register is cleared to 0000h. <4> then, the timer f/f is inverted during the same inte rval and a square wave is output from the to2 pin. frequency = 1/2t (n + 1): n = 0000h to ffffh chapter 8 8-bit timer/event counters 2 to 5 user?s manual u15905ej2v1ud 258 8.4.8 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because 8-bit timer counter n (tmn) is started asynchronously to the count pulse. figure 8-8. start timing of timer n 00h timer start 01h 02h 03h 04h count pulse tmn count value remark n = 2 to 5 user?s manual u15905ej2v1ud 259 chapter 9 real-time counter function 9.1 function the real-time counter ha s the following functions. ? week, day, hour, minute, and second counters that can count up to 4,095 weeks ? week, day, hour, minute, and second counters can be read while they are operating/stopped ? generates overflow interrupt request signal (introv) from week counter. ? generates interval interrupt request signal (intrtc) at in tervals of 0.015625, 0.03125, 0.0625, 0.125, 0.25, 0.5, or 1 second, 1 minute, 1 hour, or 1 day. the configuration of t he real-time counter function is shown below. figure 9-1. block diagram of real-time counter selector selector count enable/ disable circuit sub-count register (subc) (15 bits) prescaler 3 second count register (sec) (6 bits) internal bus second count setting register (secb) minute count setting register (miinb) hour count setting register (hourb) day count setting register (dayb) week count setting register (weekb) minute count register (min) (6 bits) hour count register (hour) (5 bits) day count register (day) (3 bits) week count register (week) (12 bits) introv intrtc 1 second 6 0.015625/0.03125/0.0625/0.125/0.25/0.5 second 1 minute 1 hour 1 day count clock = 32.768 khz f xt f brg remark f brg : prescaler 3 clock frequency (refer to 6.5 prescaler 3 .) f xt : subclock frequency chapter 9 real-time counter function user?s manual u15905ej2v1ud 260 9.2 control registers the registers listed in the table bel ow control the real-time counter. table 9-1. control registers of real-time counter register name function instruction unit reset value r/w rtcc0 rtc control register 0 8/1-bit instruction 80h r/w rtcc1 rtc control register 1 8/1-bit instruction 8xh r/w subc sub-count register 8/16-bit instruction undefined r sec second count register 8-bit instruction undefined r min minute count register 8-bit instruction undefined r hour hour count register 8-bit instruction undefined r day day count register 8-bit instruction undefined r week week count register 8/16-bit instruction undefined r secb second count setting register 8-bit instruction 00h w minb minute count setting register 8-bit instruction 00h w hourb hour count setting register 8-bit instruction 00h w dayb day count setting register 8-bit instruction 00h w weekb week count setting register 8/16-bit instruction 0000h w (1) rtc control register 0 (rtcc0) the rtcc0 register is an 8-bit register that controls the operation of the real-time counter. this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. rtcc0 stops rtc clock operation and resets sub-count value. enables rtc clock operation. rtcae 0 1 enables/disables rtc operation selects subclock (f xt ) as input clock. selects main clock (f x ) divided by prescaler 3 (f brg ) note as input clock. cks 0 1 selects input clock after reset: 80h r/w address: fffff6e0h rtcae cks 0 0 0 0 0 0 0 1 2 3 4 5 6 <7> note refer to 6.5 prescaler 3 . f brg is used alternately as the a/d converter clock. when using f brg as the clock of the real-time counter, set the fr1 and fr0 bits of the a/d co nverter mode register (adm) to other than 11. chapter 9 real-time counter function user?s manual u15905ej2v1ud 261 (2) rtc control register 1 (rtcc1) the rtcc1 register is an 8-bit register that controls the operation of the real-time counter. this register can be read or written in 8-bit or 1-bit units. this register is set to 8xh after reset. rtcc1 disables rtc count operation. enables rtc count operation. rtce 0 1 enables/disables rtc count-up operation count operation is stopped count-up operation is in progress. rtcf 0 1 rtc operation flag does not generate interrupt request signal. generates interrupt request signal every 0.015625 second. generates interrupt request signal every 0.03125 second. generates interrupt request signal every 0.0625 second. generates interrupt request signal every 0.125 second. generates interrupt request signal every 0.25 second. generates interrupt request signal every 0.5 second. generates interrupt request signal every 1 second. generates interrupt request signal every 1 minute . generates interrupt request signal every 1 hour . generates interrupt request signal every 1 day . setting prohibited ints3 0 0 0 0 0 0 0 0 1 1 1 specifies interrupt request signal generation timing other than above ints2 0 0 0 0 1 1 1 1 0 0 0 ints1 0 0 1 1 0 0 1 1 0 0 1 ints0 0 1 0 1 0 1 0 1 0 1 0 after reset: 8xh note 1 r/w address: fffff6e1h rtce ints3 ints2 ints1 ints0 0 0 rtcf note 2 <0> 1 2 3 4 5 6 <7> notes 1. 80h or 81h, depending on the value of the rtcf bit. 2. the rtcf bit is a read-only bit. remark the timing of generating an interrupt request set by the ints3 to ints0 bits is determined by the setting of the cks bit of the rtcc0 register, as follows. when cks bit = 0 f xt = 32.768 khz when cks bit = 1 f brg = 32.768 khz chapter 9 real-time counter function user?s manual u15905ej2v1ud 262 (3) sub-count register (subc) the subc register is a 15-bit regist er that counts the reference time of the real-time counter. it counts 1 second using the 32.768 khz clock. this register is read-only, in 16-bit or 8-bit units. this register is not initialized after reset or when rtce = 0. subc after reset: undefined r address: fffff6e2h 0 subc14 to subc0 0 15 14 (4) second count register (sec) this 8-bit register uses a value of 0 to 59 (decimal) to indicate the count value in seconds. this register is read-only, in 8-bit units. this register is not initialized after reset or when rtce = 0. sec after reset: undefined r address: fffff6e4h 0 0 sec5 sec4 sec3 sec2 sec1 sec0 0 1 2 3 4 5 6 7 (5) second count setting register (secb) this is an 8-bit register for setting the second count. this register is read-only, in 8-bit units. set a count value in a range of 0 to 59 (decimal) to this register. do not set a count value of 60 (decimal) or greater. this register is cleared to 00h after reset. secb after reset: 00h w address: fffff6eah 0 0 sec5 sec4 sec3 sec2 sec1 sec0 0 1 2 3 4 5 6 7 chapter 9 real-time counter function user?s manual u15905ej2v1ud 263 (6) minute count register (min) this 8-bit uses a value of 0 to 59 (decimal) to indicate the count value in minutes. this register is read-only, in 8-bit units. this register is not initialized after reset or when rtce = 0. min after reset: undefined r address: fffff6e5h 0 0 min5 min4 min3 min2 min1 min0 0 1 2 3 4 5 6 7 (7) minute count setting register (minb) this is an 8-bit register for setting the minute count. th is register is read-only, in 8-bit units. set a count value in a range of 0 to 59 (decimal) to this register. do not set a count value of 60 (decimal) or greater. this register is cleared to 00h after reset. minb after reset: 00h w address: fffff6ebh 0 0 min5 min4 min3 min2 min1 min0 0 1 2 3 4 5 6 7 (8) hour count register (hour) this 8-bit register uses a value of 0 to 23 (decimal) to in dicate the count value in hours. this register is read- only, in 8-bit units. this register is not initialized after reset or when rtce = 0. hour after reset: undefined r address: fffff6e6h 0 0 0 hour4 hour3 hour2 hour1 hour0 0 1 2 3 4 5 6 7 chapter 9 real-time counter function user?s manual u15905ej2v1ud 264 (9) hour count setting register (hourb) this is an 8-bit register for setting the hour count. this re gister is read-only, in 8-bit units. set a count value in a range of 0 to 23 (decimal) to this register. do not set a count value of 24 (decimal) or greater. this register is cleared to 00h after reset. hourb after reset: 00h w address: fffff6ech 0 0 0 hour4 hour3 hour2 hour1 hour0 0 1 2 3 4 5 6 7 (10) day count register (day) this 8-bit register used a value of 0 to 6 (decimal) to indicate the count value in days. this register is read- only, in 8-bit units. this register is not initialized after reset or when rtce = 0. day after reset: undefined r address: fffff6e7h 0 0 0 0 0 day2 day1 day0 0 1 2 3 4 5 6 7 (11) day count setting register (dayb) this is an 8-bit register for setting the day count. this re gister is read-only, in 8-bit units. set a count value in a range of 0 to 6 (decimal) to this register. do not set a count value of 7 (decimal) or greater. this register is cleared to 00h after reset. dayb after reset: 00h w address: fffff6edh 0 0 0 0 0 day2 day1 day0 0 1 2 3 4 5 6 7 chapter 9 real-time counter function user?s manual u15905ej2v1ud 265 (12) week count register (week) this 16-bit register uses a value of 0 to 4,095 (decimal) to indicate the count value in weeks. this register is read-only, in 8-bit or 16-bit units. this register is not initialized after reset or when rtce = 0. week after reset: undefined r address: fffff6e8h 0000 week11 to week0 0 15 12 11 (13) week count setting register (weekb) this is a 16-bit register for setting the week count. this register is read-only, in 8-bit or 16-bit units. set a count value in a range of 0 to 4,095 (decimal) to this register. this register is cleared to 0000h after reset. weekb after reset: 0000h w address: fffff6edh 0000 week11 to week0 0 15 12 11 chapter 9 real-time counter function user?s manual u15905ej2v1ud 266 9.3 operation 9.3.1 initializing counter and count-up <1> when the reset signal is asserted (0), the values of rtc control registers 0 and 1 (rtcc0 and rtcc1) are initialized. real-time counter clock operation is enable d when rtcae of the rtcc0 register is set to 1, and real-time counter count operation is enabled w hen rtce of the rtcc1 register is set to 1. <2> the sub-count register (subc) is reset if the r eal-time count clock operation is stopped when rtcae is 0. <3> the real-time counter clock operation is stopped w hen the cks bit of the rtcc0 register is selected and rtcae is set to 1. <4> after 3 internal clocks, the values of all the count setting registers are reflected on the corresponding count registers at all once, and each c ount register starts counting up. <5> each time a count register overflows, the higher count register starts counting up. <6> at the clock after the one at which the overflow condit ions of all the count registers have been satisfied, all the count registers are cleared to ?0?. the introv signal is asserted active for the duration of one cycle of the real-time count clock after the week count register (week) overflows. 9.3.2 rewriting counter <1> when the reset signal is asserted (0), the values of the rtcc0 and rtcc1 registers are initialized. real- time counter clock operation is enabled when rtcae is set to 1, and real-time counter count operation is enabled when rtce is set to 1. <2> write a value to each count setting register. <3> the value of all the count setting registers are re flected on the corresponding count registers all at once two internal clocks after rtce is set to 1, and the real-time counter starts counting up 3 internal clocks after that. chapter 9 real-time counter function user?s manual u15905ej2v1ud 267 9.3.3 controlling interrupt request signal output this section explains how to control interrupt request signals, taking ints0 to ints3 = 0111b (every second) and ints0 to ints3 = 1000b (every minute) as an example. <1> when the reset signal is asserted (0), the values of the rtcc0 and rtcc1 registers are initialized. real- time counter clock operation is enabled when rtcae is set to 1, and real-time counter count operation is enabled when rtce is set to 1. <2> clear rtcae to 0 and select the cks bit. <3> the internal clock operation is started when rtcae = 1. <4> after 3 internal clocks, the value of all the count setting registers are reflected on the corresponding count registers at all once, and the real -time counter starts counting up. <5> set the ints0 to ints 3 bits to 0111b (1000b). <6> because ints0 to ints3 = 0111b, the intrtc signal is asserted each time 1 second is counted (because ints0 to ints3 = 1000b, the intrtc signal is asserted each time 1 minute is counted). <7> the introv signal is asserted when the overflow c onditions of all the count r egisters have been satisfied. 9.3.4 notes (1) when the reset signal is input, the cks bit of rtc cont rol register 0 (rtcc0) is cleared to 0. therefore, the real-time counter operates with the subclock (f xt ). note the following points. ? to continue the real-time counter operation even during the reset period, select f xt (cks = 0) as the count clock. if the prescaler 3 clock (f brg ) (cks = 1) is selected, the count clock is changed to f xt (cks = 0) by the reset input, in which case the operation cannot be guaranteed. ? if the real-time counter is not used, clear rtcae of the rtcc0 register to 0 after the reset signal has been cleared. (2) perform initialization after clearing rtcae to 0 when the reset signal has been cleared for the first time. for initialization, set each count setting register, count cloc k, and interrupt request signal generation timing using the procedure described in (4) and (5) below, and clear the ovfif bit of the ovfic register and the rtcif bit of the rtcic register to 0. (3) read each count register us ing the following procedure: <1> read the second, minute, hour, day, and week co unt registers in that order, and then read the second count register again. <2> compare the value of the second count register read first with the val ue of the second count register read second. if the two values do not match, the chances are that the counter counted up while it was being read. if so, repeat steps <1> and <2> again. chapter 9 real-time counter function user?s manual u15905ej2v1ud 268 (4) write data to each count setting register using the following procedure: ? to clear the sub-count register (subc) <1> using the procedure described in (3) above, read the values of all the c ount registers (this may be omitted), and clear rtcae to 0. <2> write a value to one of the count setting registers. write the value read in step <1> to the other count setting registers. <3> set rtcae to 1. the values of the count setti ng registers will be transferred to the count registers, and the real-time counter will start c ounting (after 2 or 3 count clocks). ? to not clear the sub-count register (subc) (to hold the value) <1> clear rtce of rtc control register 1 (rtcc1) to 0, and check if rtcf of the rtcc1 register is cleared to 0 (count stops). <2> read the values of all the count registers (this may be omitted). <3> write a value to one of the count setting registers. write the va lue read in <2> to the other count setting registers. <4> set rtce to 1. the values of the count setting registers will be transferred to the count registers, and the real-time counter will start c ounting (after 2 or 3 count clocks). (5) before changing the interrupt request signal generati on timing or changing the rtcae bit from 1 to 0, set the ovfmk bit of the ovfic register and the rtcmk bit of the rtcic register to 1, and after changing the generation timing or rtcae bit, clear the ovfif bit of the ovfic register and the rtcif bit of the rtcic register to 0. (6) to change the count clock, be sure to clear rtace to 0. (7) after releasing reset, clear the ov fif bit of the ovfic register and the rt cif bit of the rtcic register to 0. user?s manual u15905ej2v1ud 269 chapter 10 watchdog timer functions 10.1 functions the watchdog timer has the following operation modes. ? watchdog timer ? interval timer ? selecting the oscillation stabilization time the following functions are realized fr om the above-listed operation modes. ? generation of non-maskable interrupt request si gnal (intwdt) upon overflow of watchdog timer ? generation of system reset signal upon overflow of watchdog timer ? generation of maskable interrupt request signal (intwdtm) upon overflow of interval timer ? securing of oscillation stabilization time for main system clock remark select whether to use the watchdog timer in the wa tchdog timer mode or the interval timer mode using watchdog timer mode register (wdtm). chapter 10 watchdog timer functions user?s manual u15905ej2v1ud 270 figure 10-1. block diagram of watchdog timer oscmd 13-bit division circuit run osts0 to osts2, wdcs0 to wdcs2 wdtm3, wdtm4 clear clear 8-bit counter output control f xw f xw /2 13 f xw /2 12 f xw /2 11 f xw /2 10 f xw /2 9 f xw /2 8 f xw /2 7 f xw /2 6 f xw /2 5 selector ovf intwdtm intwdt wdtres ostovf remark intwdtm: request signal for maskable interrupt through wdt overflow intwdt: request signal for non-maskable interrupt through wdt overflow wdtres: reset signal through wdt overflow ostovf: oscillation stabilization timer overflow signal oscmd: oscillation stabilization timer mode signal f xw : watchdog timer clock frequency ? while oscillation stabilization time is being counted: f xw = f x /2 ? other than above: f xw = f xx /2 chapter 10 watchdog timer functions user?s manual u15905ej2v1ud 271 10.2 configuration the watchdog timer consists of the following hardware. table 10-1. configuration of watchdog timer item configuration control register oscillation stabilization time selection register (osts) watchdog timer clock select ion register (wdcs) watchdog timer mode register (wdtm) 10.3 control registers the registers that control the watchdog timer are as follows. ? oscillation stabilization time selection register (osts) ? watchdog timer clock selection register (wdcs) ? watchdog timer mode register (wdtm) (1) oscillation stabilization time selection register (osts) this register selects the oscillati on stabilization time following reset or release of the stop mode. the osts register can be read or written in 8-bit units. this register is set to 04h after reset. 0 osts 0 0 0 0 osts2 osts1 osts0 2 14 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 19 /f x 2 20 /f x 2 21 /f x 2 22 /f x osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 13.5 mhz 8 mhz 2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms 17 mhz 3.855 ms 7.710 ms 15.42 ms 30.84 ms 61.68 ms 123.4 ms 246.7 ms 4.855 ms 9.709 ms 19.42 ms 38.84 ms 77.67 ms 155.3 ms 310.7 ms f x after reset: 04h r/w address: fffff6c0h setting prohibited setting prohibited 20 mhz 3.28 ms 6.55 ms 13.1 ms 26.2 ms 52.4 ms 105 ms 210 ms setting prohibited caution set the oscillation stabilizat ion time to 1.5 ms or longer. chapter 10 watchdog timer functions user?s manual u15905ej2v1ud 272 (2) watchdog timer clock selection register (wdcs) this register sets the overflow time of the watchdog timer and the interval timer. the wdcs register can be read or written in 8-bit units. this register is cleared to 00h after reset. 0 wdcs 0 0 0 0 wdcs2 wdcs1 wdcs0 wdcs2 0 0 0 0 1 1 1 1 overflow time of watchdog timer/interval timer wdcs1 0 0 1 1 0 0 1 1 wdcs0 0 1 0 1 0 1 0 1 after reset: 00h r/w address: ffff6c1h 2 14 /f xx 2 15 /f xx 2 16 /f xx 2 17 /f xx 2 18 /f xx 2 19 /f xx 2 20 /f xx 2 22 /f xx 13.5 mhz 8 mhz 2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms 17 mhz 964 s 1.928 ms 3.855 ms 7.710 ms 15.42 ms 30.84 ms 61.68 ms 246.7 ms 1.214 ms 2.427 ms 4.855 ms 9.709 ms 19.42 ms 38.84 ms 77.67 ms 310.7 ms f x 20 mhz 819 s 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 209.7 ms remark f xx : main clock frequency chapter 10 watchdog timer functions user?s manual u15905ej2v1ud 273 (3) watchdog timer mode register (wdtm) this register sets the watchdog timer operati on mode and enables/disables count operations. this register is a special register that can be written only in a special sequence (refer to 3.4.8 special registers ). the wdtm register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. run stops counting clears counter and starts counting run 0 1 selection of watchdog timer operation mode note 1 wdtm 0 0 wdtm4 wdtm3 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (upon overflow, maskable interrupt intwdtm is generated.) watchdog timer mode 1 (upon overflow, non-maskable interrupt intwdt is generated.) watchdog timer mode 2 (upon overflow, reset operation wdtres is started.) wdtm4 0 0 1 1 wdtm3 0 1 0 1 selection of watchdog timer operation mode note 2 < > notes 1. once the run bit is set (to 1), it cannot be cleared (to 0) by software. therefore, when counting is st arted, it cannot be stoppe d except by reset (reset input or watchdog timer overflow). 2. once the wdtm3 and wdtm4 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only by reset. chapter 10 watchdog timer functions user?s manual u15905ej2v1ud 274 10.4 operation 10.4.1 operation as watchdog timer watchdog timer operation to detect a program loop is sele cted by setting bit 4 (wdtm4) of the watchdog timer mode register (wdtm) to 1. the count clock (program loop detection time interval) of the watchdog timer can be selected with bits wdcs0 to wdcs2 of the watchdog timer clock selection register (wdcs) . the count operation is started by setting bit 7 (run) of the wdtm register to 1. when, after the count operat ion is started, the run bit is again set to 1 within the set program loop detection time interval, the watchdog time r is cleared and the count operation starts again. if the program loop detection time is exceeded without the run bit being set to 1, a reset (wdtres) or a non- maskable interrupt request signal (i ntwdt) is generated, depending on the value of bit wdtm3 of the wdtm register. the count operation of the watchdog ti mer stops in the software stop mode a nd idle mode. therefore, set the run bit to 1 before the software stop mode or idle mode is entered in order to clear the watchdog timer. because the watchdog timer operates in the halt mode, do not use the watchdog timer when using the halt mode. caution once the wdtm4 bit is cleared to 0 (thereb y selecting the interval timer mode), the watchdog timer mode is not entered as long as a reset does not occur. when the subclock is selected for the cpu clock, the count operation of the watchdog timer stops (the value of the watchdog timer is maintained). table 10-2. program loop detection time of watchdog timer program loop detection time clock f xx = 20 mhz f xx = 17 mhz f xx = 13.5 mhz f xx = 8 mhz 2 14 /f xx 819 s 964 s 1.214 ms 2.048 ms 2 15 /f xx 1.638 ms 1.928 ms 2.427 ms 4.096 ms 2 16 /f xx 3.277 ms 3.855 ms 4.855 ms 8.192 ms 2 17 /f xx 6.554 ms 7.710 ms 9.709 ms 16.38 ms 2 18 /f xx 13.11 ms 15.42 ms 19.42 ms 32.77 ms 2 19 /f xx 26.21 ms 30.84 ms 33.84 ms 65.54 ms 2 20 /f xx 52.43 ms 61.68 ms 77.67 ms 131.1 ms 2 22 /f xx 209.7 ms 246.7 ms 310.7 ms 524.3 ms remark f xx : main clock frequency chapter 10 watchdog timer functions user?s manual u15905ej2v1ud 275 10.4.2 operation as interval timer the watchdog timer can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by setting bi t 4 (wdtm4) of the watchdog timer mode register (wdtm) to 0. when the watchdog timer operates as an interval timer, th e interrupt mask flag (wdtmk) and priority specification flags (wdtpr0 to wdtpr2) of the wdtic register are va lid and maskable interrupt request signals (intwdtm) can be generated. the default priority of the intwdtm signal is set to the highest level among the maskable interrupt request signals. the interval timer continues to operate in the halt m ode, but it stops operating in the software stop mode and the idle mode. therefore, set the run bit of the wdtm register to 1 befor e the software stop mode or idle mode is entered in order to clear the interval timer. cautions 1. once the wdtm4 bit is set to 1 (thereby selecting the watchdog timer mode), the interval timer mode is not entered as long as a reset does not occur. 2. when the subclock is selec ted for the cpu clock, the count operation of the watchdog timer stops (the value of the watchdog timer is maintained). table 10-3. interval time of interval timer interval time clock f xx = 20 mhz f xx = 17 mhz f xx = 13.5 mhz f xx = 8 mhz 2 14 /f xx 819 s 964 s 1.214 ms 2.048 ms 2 15 /f xx 1.638 ms 1.928 ms 2.427 ms 4.096 ms 2 16 /f xx 3.277 ms 3.855 ms 4.855 ms 8.192 ms 2 17 /f xx 6.554 ms 7.710 ms 9.709 ms 16.38 ms 2 18 /f xx 13.11 ms 15.42 ms 19.42 ms 32.77 ms 2 19 /f xx 26.21 ms 30.84 ms 33.84 ms 65.54 ms 2 20 /f xx 52.43 ms 61.68 ms 77.67 ms 131.1 ms 2 22 /f xx 209.7 ms 246.7 ms 310.7 ms 524.3 ms remark f xx : main clock frequency chapter 10 watchdog timer functions user?s manual u15905ej2v1ud 276 10.4.3 oscillation stabilization time selection function the wait time until the oscillation st abilizes after the stop mode is releas ed is controlled by the oscillation stabilization time register (osts). the osts register is set by an 8-bit memory manipulation instruction. this register is set to 04h after reset. 0 osts 0 0 0 0 osts2 osts1 osts0 2 14 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 19 /f x 2 20 /f x 2 21 /f x 2 22 /f x osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 13.5 mhz 8 mhz 2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms 17 mhz 3.855 ms 7.710 ms 15.42 ms 30.84 ms 61.68 ms 123.4 ms 246.7 ms 4.855 ms 9.709 ms 19.42 ms 38.84 ms 77.67 ms 155.3 ms 310.7 ms f x after reset: 04h r/w address: fffff6c0h setting prohibited setting prohibited 20 mhz 3.28 ms 6.55 ms 13.1 ms 26.2 ms 52.4 ms 105 ms 210 ms setting prohibited cautions 1. the wait time followi ng release of the software stop mode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the software stop mode, regardless of whether the stop mode is released by r eset or the occurrence of an interrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to set bits 3 to 7 to 0. 3. set the oscillation stabilization time to 1.5 ms or longer. 4. the oscillation stabilization ti me following reset release is 2 19 /f x (because the initial value of the osts register = 04h). remark f x = main clock oscillation frequency user?s manual u15905ej2v1ud 277 chapter 11 a/d converter 11.1 function the a/d converter converts analog input signals into digita l values with a resolution of 10 bits. in the v850es/sa2, it has a 12-channel (ani0 to ani11) configuration, and in the v850es/sa3, it has a 16-channel (ani0 to ani15) configuration. the features of the a/d converter are shown below. 10-bit resolution 12 channels (v850es/sa2) 16 channels (v850es/sa3) successive approximation method power fail detection function operating voltage: av dd = av ref0 = 2.2 to 2.7 v analog input voltage: av ss to av ref0 conversion rate: 8.2 to 150 s the block diagram is shown below. figure 11-1. block diagram of a/d converter comparator av ref0 av dd av ss intad analog input side c array reference side c array controller successive approximation register (sar) a/d conversion result register (adcr) selector ads0 to ads3 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 ani12 note ani13 note ani14 note ani15 note note v850es/sa3 only chapter 11 a/d converter user?s manual u15905ej2v1ud 278 figure 11-2. block diagram of power fail detection function a/d converter comparator power fail comparison threshold register (pft) selector selector ads0 to ads3 pfcm pfen intad ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 ani12 note ani13 note ani14 note ani15 note note v850es/sa3 only chapter 11 a/d converter user?s manual u15905ej2v1ud 279 11.2 configuration the a/d converter consists of the following hardware. table 11-1. configuration of a/d converter item configuration analog input 12 channels (ani0 to ani11): v850es/sa2 16 channels (ani0 to ani15): v850es/sa3 registers successive appro ximation register (sar) a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read power fail comparison threshold register (pft) control registers a/d converter mode register (adm) analog input channel specification register (ads) power fail comparison mode register (pfm) (1) successive approximation register (sar) this register compares the voltage value of the analog input signal wit h the voltage tap (compare voltage) value from the series resistor string, and holds the co mparison result starting from the most significant bit (msb). when the comparison result has been saved down to the least significant bit (lsb) (a/d conversion completion), the contents of the sar are transferr ed to the a/d conversion result register. (2) a/d conversion result register (adcr) , a/d conversion result register (adcrh) each time a/d conversion has been completed, the result of the conversion is loaded to this register from the successive approximation register, and the higher 10 bits of this register hold the re sult of the a/d conversion (the lower 6 bits are fixed to 0). the adcr register is read-only, in 16-bit units. adcr is undefined after reset. when using only the higher 8 bits of the a/d conversion result, the adcrh register is read-only, in 8-bit units. caution when data is written to the a/d conver ter mode register (adm) or analog input channel specification register (ads), the contents of the adcr register may become undefined. read the conversion result after comp letion of conversion and before writing data to the adm and ads registers. otherwise, the correct conversion result may not be read. (3) power fail comparison th reshold register (pft) this register sets the threshold when compar ing with the a/d conversion result register. the 8-bit data set in the pft register and the higher 8 bits (adcrh) of the a/d conversion result register are compared. the pft register can be read or written in 8-bit units. this register is cleared to 00h after reset. (4) sample & hold circuit the sample & hold circuit samples each of the analog i nput signals sequentially sent from the input circuit and sends the sampled data to the voltage comparator. this circuit holds the sampled analog input voltage during a/d conversion. chapter 11 a/d converter user?s manual u15905ej2v1ud 280 (5) voltage comparator the voltage comparator compar es the analog input signal with the output vo ltage of the series resistor string. (6) series resistor string the series resistor string is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (7) ani0 to ani15 pins note these are analog input pins for the 16 channels note of the a/d converter that are used to input analog signals to be converted into digital signals. pins other than t hose selected as analog input with the analog input channel specification register (ads) can be used as input ports. note the v850es/sa2 provides only 12 channels, ani0 to ani11. caution make sure that the voltag e input to ani0 to ani 15 does not exceed the rated values. if a voltage higher than av ref0 or lower than av ss (even within the absolute maximum ratings) is input to a channel, the conversion value of the channel is undefined and the conversion values of the other channels may also be affected. (8) av ref0 pin this is the reference voltage input pin of the a/d converter. t he signals input to the ani0 to ani15 or ani0 to ani11 pins are converted into digital si gnals based on the voltage applied across av ref0 and av ss . (9) av dd pin this is the analog power supply pin of the a/d c onverter. always use the same potential as the v dd pin even when not using the a/d converter. (10) av ss pin this is the ground potential pin of the a/d conver ter. always use the same potential as the v ss pin even when not using the a/d converter. chapter 11 a/d converter user?s manual u15905ej2v1ud 281 11.3 control registers the a/d converter is controlled by the following registers. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? power fail comparison mode register (pfm) chapter 11 a/d converter user?s manual u15905ej2v1ud 282 (1) a/d converter mode register (adm) this register sets the conversion time of the analog inpu t signal to be converted into a digital signal as well as conversion start and stop. the adm register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. adcsb note 1 adcs note 1 0 1 stops conversion enables conversion a/d conversion control adm 0 fr3 note 2 fr2 note 2 fr1 fr0 0 0 fr3 note 2 0 0 1 1 fr2 note 2 0 1 0 1 19 clocks setting prohibited setting prohibited setting prohibited number of a/d conversion clocks fr1 0 0 1 1 fr0 0 1 0 1 f xx /16 f xx /8 f xx /4 clock of prescaler 3 (f brg ) a/d conversion clock after reset: 00h r/w address: fffff200h < > notes 1. f brg output (refer to 6.5 prescaler 3 ) is alternated with the main clock divider of the real-time counter. to use f brg output as the conversion clock of the a/d co nverter, therefore, clear the cks bit of rtc control register 0 (rtcc0) (refer to 9.2 (1) ) to 0. an a/d conversion operation can be used to output the f brg clock in the idle mode. to reduce the power consumption, clear the ce bit of the prescaler mode register (prsm) (refer to 6.5.1 (1) ) and adcs bit of the adm register to 0. 2. be sure to clear the fr3 and fr2 bits to 00. caution be sure to clear bits 6, 1, and 0 to 0. remark refer to tables 11-2 and 11-3 for examples of setting the a/d conversion time. chapter 11 a/d converter user?s manual u15905ej2v1ud 283 table 11-2. example of setting a/d conversion ti me (immediately after setting adcs bit to 1) fr3 fr2 fr1 fr0 a/d conversion time f xx = 20 mhz f xx = 17 mhz f xx = 13.5 mhz f xx = 8 mhz f xx = 2 mhz 0 0 0 0 392/f xx 19.6 s 23.1 s 29.1 s 49 s setting prohibited 0 0 0 1 196/f xx 9.8 s 11.6 s 14.6 s 24.5 s 98 s 0 0 1 0 98/f xx setting prohibited setting prohibited setting prohibited 12.3 s 49 s 0 0 1 1 147/f xx note setting prohibited 8.7 s 10.9 s 18.4 s 73.5 s other than above setting prohibited note when prsm = 10h, prscm = 03h (refer to 6.5 prescaler 3 .) cautions 1. set the a/d conversion ti me within the range of 8.2 to 150 s. the operation is not guaranteed if this range is exceeded. 2. clear the fr3 and fr2 bits to 00. table 11-3. example of setting a/d conv ersion time (second and subsequent time) fr3 fr2 fr1 fr0 a/d conversion time f xx = 20 mhz f xx = 17 mhz f xx = 13.5 mhz f xx = 8 mhz f xx = 2 mhz 0 0 0 0 320/f xx 16.0 s 18.9 s 23.8 s 40 s setting prohibited 0 0 0 1 160/f xx 8.0 s 9.5 s 11.9 s 20 s 80 s 0 0 1 0 80/f xx setting prohibited setting prohibited setting prohibited 10 s 40 s 0 0 1 1 120/f xx note setting prohibited 7.1 s 8.9 s 15 s 60 s other than above setting prohibited note when prsm = 10h, prscm = 03h (refer to 6.5 prescaler 3 .) chapter 11 a/d converter user?s manual u15905ej2v1ud 284 (2) analog input channel specification register (ads) this register specifies the analog volt age input port to be a/d converted. the ads register can be read or written in 8-bit units. this register is cleared to 00h after reset. 0 ads 0 0 0 ads3 ads2 ads1 ads0 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 ani12 note ani13 note ani14 note ani15 note setting prohibited ads3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ads2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ads1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ads0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 specification of analog input channel after reset: 00h r/w address: fffff201h other than above note the ani12 to ani15 channels are available only in the v850es/sa3. in the v850es/sa2, setting these channels is prohibited. chapter 11 a/d converter user?s manual u15905ej2v1ud 285 (3) power fail comparison mode register (pfm) this register sets the power fail monitoring mode. it compares the value of the power fail comparison threshold register (pft) and the value of the a/d conversion result register (adcrh). the pfm register can be read or wri tten in 8-bit or 1-bit units. this register is cleared to 00h after reset pfen pfen 0 1 disables power fail comparison enables power fail comparison selection of power fail comparison enable/disable pfm pfcm 0 0 0 0 0 0 pfcm 0 1 generates interrupt request signal (intad) when adcr pft generates interrupt request signal (intad) when adcr < pft selection of power fail comparison mode after reset: 00h r/w address: fffff202h (4) power fail comparison thr eshold value register (pft) this register sets the value to be com pared in the power fail comparison mode. the 8-bit data set in the pft register and the higher 8 bits (adcrh) of the a/d conversion result register are compared. the pft register can be read or written in 8-bit units. this register is cleared to 00h after reset. pft after reset: 00h r/w address: fffff203h chapter 11 a/d converter user?s manual u15905ej2v1ud 286 (5) a/d conversion result register, a/d co nversion result register h (adcr, adcrh) these registers store the a/d conversion results. these registers are read-only, in 16-bit or 8-bit units. specify the adcr register when accessing in 16-bit units and specify the adcrh register when accessing in 8- bit units. in the adcr register, 10 bits of the conversion result are read from the hi gher 10 bits and 0 is read from the lo wer 6 bits. in the adcrh register, the higher 8 bits of the conversion result are read. the values of these registers are undefined after reset. after reset: undefined r address: fffff204h adcr ad9 ad8 ad7 ad6 ad0 0 0 0 0 0 0 ad1 ad2 ad3 ad4 ad5 ad9 adcrh ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: fffff205h chapter 11 a/d converter user?s manual u15905ej2v1ud 287 the following relationship exists between the analog input voltage input to the analog input pins (ani0 to ani11 or ani0 to ani15) and the a/d conversion re sults (a/d conversion result register (adcr)). v in sar = int ( av ref0 1024 + 0.5) adcr note = sar 64 or av ref0 av ref0 (sar ? 0.5) 1024 v in < (sar + 0.5) 1024 int ( ): function that returns the inte ger portion of the value in parentheses v in : analog input voltage av ref0 : av ref0 pin voltage adcr: value of a/d conversion result register n (adcr) caution the lower 6 bits of adcr are fixed to 0. the following shows the relationship between the ana log input voltage and a/ d conversion results. figure 11-3. relationship between analog input voltage and a/d conversion results 1023 1022 1021 ffc0h ff80h ff40h 3 2 1 0 00c0h 0080h 0040h 0000h input voltage/av ref0 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 a/d conversion results (adcr) sar adcr chapter 11 a/d converter user?s manual u15905ej2v1ud 288 11.4 operation 11.4.1 conversion operation ? setting adcs of the a/d converter mode register (adm) to 1 starts conversion of the signal input to the channel specified by the analog input channel specification register (ads). u pon completion of the conversion, the conversion result is stored in the a/d conversion re sult register (adcr) and a new conversion starts. ? if adm, ads, the power fail comparison threshold regi ster (pft), or the power fail comparison mode register (pfm) is written during conversion, conversion is interrupt ed and the conversion operation starts again from the beginning. ? if adcs is set to 0 during conversion, conversion is interrupted and the conversion operation is stopped. ? for whether or not the conversion end interrupt request signal (intad) is generated, refer to 11.4.2 . 11.4.2 conversion operation (pow er fail monitoring function) the conversion end interrupt request signal (intad) ca n be controlled as follows using the pfm and pft registers. table 11-4. intad signal control pfm register pfen bit pfcm bit operation 0 don?t care intad signal is output each time a/d conversion ends 1 0 intad signal is output only if conversion result (adcrh) pft 1 1 intad signal is output only if conversion result (adcrh) < pft remark when pfen = 1, because the conversion result is overwritten after intad has been output unless the conversion result is read by the time the next conversion ends, in some cases it may appear as if the actual operation differs fr om the operation described above (refer to figure 11-4 ). figure 11-4. power fail monitoring function (pfcm = 0) conversion operation adcr pft intad ani0 80h 80h 7fh 80h ani0 ani0 ani0 note note if reading is not performed during this interval, the conversion result changes to the next conversion result. chapter 11 a/d converter user?s manual u15905ej2v1ud 289 11.5 notes on use ? do not read the p7 register during a/d conversion. ? do not change the set value of t he adm register during a/d conversion (adcs bit = 1). before changing the value, clear the adcs bit to 0. the operation is not guaranteed when the value is changed with the adcs bit set to 1. ? when not using the a/d converter in the standby mode, clear the adcs bit to 0, then change to the standby mode. connecting the av ref0 pin to v ss further reduces the power consumpti on. if the supply clock to the a/d converter stops with the adcs bit set to 1 (i.e., in idle (the fr1 and fr0 bits of t he adm register are not 11b) or software stop mode), each register stops operatio n holding the value immediately before the clock was stopped. the first a/d conversion operation after the clock supply is resumed cannot be guaranteed. chapter 11 a/d converter user?s manual u15905ej2v1ud 290 11.6 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that can be recognized, i. e., the ratio of the analog input voltage to 1 bit of digital output, is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of the range of convertible analog input voltages expressed as a percentage, and can be expressed as foll ows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref ? 0)/100 = av ref /100 where the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between t he actually measured value and the theoretical value. it is the total of the zero-scale error, full-scale e rror, linearity error, and combinations of these errors. the overall error in the characteristics t able does not include the quantization error. figure 11-5. overall error ideal line overall errors 1 ...... 1 0 ...... 0 0av ref0 analog input digital output chapter 11 a/d converter user?s manual u15905ej2v1ud 291 (3) quantization error this is the error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts ana log input voltages in a range of 1/2 lsb into the same digital codes, the quantization error is unavoidable. this error is not included in the overall error, zero-scale error, full-scale error, in tegral linearity error, and differential linearity error in the characteristics table. figure 11-6. quan tization error quantization error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 11-7. zero-scale error av ref0 analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10 1 2 3 100 011 010 001 000 zero-scale errors chapter 11 a/d converter user?s manual u15905ej2v1ud 292 (5) full-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1?110 to 0?111 (full scale ? 3/2 lsb). figure 11-8. full-scale error av ref0 analog input (lsb) digital output (lower 3 bits) 111 av ref0 ? 3 0 av ref0 ? 2av ref0 ? 1 100 011 010 000 full-scale errors (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error indicates the difference between the actually measured value and its theoretical value when a specific code is output. figure 11-9. differential linearity error ideal widths of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref0 analog input digital output chapter 11 a/d converter user?s manual u15905ej2v1ud 293 (7) integral linearity error this error indicates the extent to which the conversion ch aracteristics differ from the ideal linear relations. it indicates the maximum value of the difference between t he actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 11-10. integral linearity error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output ideal line integral linearity errors (8) conversion time this is the time required to obtain a digital output after an analog input voltage has been assigned. the conversion time in the characteristics table includes sampling time. (9) sampling time this is the time during which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 11-11. sampling time sampling time conversion time user?s manual u15905ej2v1ud 294 chapter 12 d/a converter 12.1 functions the d/a converter has the following functions. { 8-bit resolution 2 channels (dac0, dac1) { r string method { conversion time: 20 s max. (av ref1 = 2.2 to 2.7 v) { analog output voltage: av ref1 m/256 (m = 0 to 255; value set to dacsn register) { operation modes: normal mo de, real-time output mode remark n = 0, 1 the d/a converter configurat ion is shown below. figure 12-1. block diagram of d/a converter dacs0 r string resistor r string resistor dacs1 ano0 ano1 dace0 dace1 dacs0 write damd0 inttm2 dacs1 write damd1 inttm3 av ref1 av ss chapter 12 d/a converter user?s manual u15905ej2v1ud 295 12.2 configuration the d/a converter consists of the following hardware. table 12-1. configuration of d/a converter item configuration control registers d/a converter mode register (dam) d/a conversion value setting regi sters 0 and 1 (dacs0 and dacs1) 12.3 control registers the registers that control the d/ a converter are as follows. ? d/a converter mode register (dam) ? d/a conversion value setting registers 0 and 1 (dacs0 and dacs1) (1) d/a converter mode register (dam) this register controls the oper ation of the d/a converter. dam can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. 0 normal mode real-time output mode note damdn 0 1 selection of d/a converter operation mode (n = 0, 1) dam 0 0 0 damd1 dace1 damd0 dace0 after reset: 00h r/w address: fffff284h disables operation enables operation dacen 0 1 d/a converter operation enable/disable control (n = 0, 1) < > < > note the output trigger in the real-time output mode (damdn bit = 1) is as follows. ? when n = 0: inttm2 signal (refer to chapter 8 8-bit timer/event counters 2 to 5 ) ? when n = 1: inttm3 signal (refer to chapter 8 8-bit timer/event counters 2 to 5 ) chapter 12 d/a converter user?s manual u15905ej2v1ud 296 (2) d/a conversion value setting registers 0 and 1 (dacs0 and dacs1) these registers set the analog voltage va lue output to the ano0 and ano1 pins. these registers can be read or written in 8-bit units. these registers are cleared to 00h after reset. da7 dacsn da6 da5 da4 da3 da2 da1 da0 after reset: 00h r/w address: dacs0 fffff280h, dacs1 fffff282h caution in the real-time output mode (damdn bit = 1), set the dacsn register before the inttm2/inttm3 signals are ge nerated. d/a conversion starts when the inttm2/inttm3 signals are generated. remark n = 0, 1 chapter 12 d/a converter user?s manual u15905ej2v1ud 297 12.4 operation 12.4.1 operation in normal mode d/a conversion is performed using a write operation to d/a conversion val ue setting register n (dacsn) as the trigger. the setting method is described below. <1> set the damdn bit of the d/a converter mode register (dam) to 0 (normal mode). <2> set the analog voltage value to be output to the anon pin to the dacsn register. steps <1> and <2> above constitute the initial settings. <3> set the dacen bit of the dam register to 1 (d/a conversion enable). d/a conversion starts when this setting is performed. <4> to perform subsequent d/a conversions, write to the dacsn register. the previous d/a conversion result is held un til the next d/a conversion is performed. remark n = 0, 1 12.4.2 operation in real-time output mode d/a conversion is performed using the interrupt reques t signals (inttm2 and inttm3) of 8-bit timer/event counters 2 and 3 (tm2 and tm3) as triggers. the setting method is described below. <1> set the damdn bit of the dam regi ster to 1 (real-time output mode). <2> set the analog voltage value to be output to the anon pin to the dacsn register. <3> set the dacen bit of the dam register to 1 (d/a conversion enable). steps <1> to <3> above constitu te the initial settings. <4> operate 8-bit timer/event counters 2 and 3 (tm2 and tm3). <5> d/a conversion starts when the inttm2 and inttm3 signals are generated. <6> the inttm2 and inttm3 signals are generated when subsequent d/a conversions are performed. before performing the next d/a conversion (gener ation of inttm2 and inttm3 signals), set the analog voltage value to be output to the anon pin to the dacsn register. chapter 12 d/a converter user?s manual u15905ej2v1ud 298 12.4.3 cautions observe the following cautions when using the d/a converter of the v850es/sa2 and v850es/sa3. (1) do not change the set value of the dacsn register while the trigger signal is being issued in the real-time output mode. (2) before changing the operation mode, be sure to clear dacen to 0. (3) when using only one channel of the d/a converter, co nnect the pins that are not used as analog outputs to v ss . (4) when using the p80/ano0 and p81/ano1 pins as port pins (when not using the d/a converter), make sure that their input level does not change much. (5) when not using the d/a converter in the standby mode , clear the dacs bit to 0, and then change to the standby mode. connecting the av ref1 pin to v ss further reduces the power consumption. (6) make sure that v dd = ev dd = av dd = av ref1 = 2.2 to 2.7 v. if this range is exceeded, the operation is not guaranteed. (7) apply power to av dd at the same timing as v dd . (8) no current can be output from the anon pin (n = 0, 1) because the output impedance of the d/a converter is high. when connecting a resistor of 5 m ? or less, insert a jfet input operational amplifier between the resistor and the anon pin. figure 12-2. external pin connection example av ref1 ev dd output 10 f 0.1 f 10 f 0.1 f av dd anon av ss ? + jfet input operational amplifier user?s manual u15905ej2v1ud 299 chapter 13 asynchronous ser ial interface n (uartn) 13.1 features ? transfer rate: 300 bps to 312.5 kbps (using a dedicated baud rate generator and an internal system clock of 20 mhz) ? full-duplex communications on-chip receive buffer register n (rxbn) on-chip transmit buffer register n (txbn) ? two-pin configuration txdn: transmit data output pin rxdn: receive data input pin ? reception error detection functions ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt (intsren): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt (intsrn): interrupt is generated when receive data is transferred from the shift register to receive buffer register n after serial transfer is completed during a reception enabled state ? transmission completion interrupt (intstn): interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the shift register is completed ? the character length of transmit/receive data is specified by the asimn register ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? on-chip dedicated baud rate generator remark n = 0, 1 chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 300 13.1.1 switching modes between uart0 and csi1 csi1 and uart0 of the v850es/sa2 and v850es/sa3 share pins, and therefore these interfaces cannot be used at the same time. select csi1 or uart0 in advance by using port mode control register 3 (pmc3) and port function control register 3 (pfc3) (refer to 4.3.3 port 3 ). caution csi1 or uart0 transmission/reception opera tions are not guaranteed if the mode is changed during transmission or reception. be sure to disable the operation of the unit that is not used. figure 13-1. selecting csi1 or uart0 mode 7 0 pmc3 6 0 5 0 4 0 3 0 2 pmc32 1 pmc31 0 pmc30 7 0 pfc3 6 0 5 0 4 0 3 0 2 0 1 pfc31 0 pfc30 after reset: 00h r/w address: fffff446h after reset: 00h r/w address: fffff466h pmc3n pfc3n operation mode 0 port i/o mode 1 0 csi1 mode 1 1 uart0 mode remark s 1. n = 0, 1 2. = don?t care chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 301 13.2 configuration uartn is controlled by asynchronous serial interface m ode register n (asimn), asynchronous serial interface status register n (asisn), and asynchro nous serial interface transmission status register n (asifn). receive data is maintained in receive buffer register n (rxbn), and transmi t data is written to transmit buffer register n (txbn). figure 13-3 shows the configuration of a synchronous serial interface n (uartn). (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register for specifying the operation of the asynch ronous serial interface. (2) asynchronous serial interfa ce status register n (asisn) the asisn register consists of a set of flags that indicate the error cont ents when a reception error occurs. the various reception error flags are set (1) when a reception error occurs and are reset (0) when the asisn register is read. (3) asynchronous serial interface tran smission status register n (asifn) the asifn register is an 8-bit regist er that indicates the status when a transmit operation is performed. this register consists of a transmit buffer data flag, which indicates the hold stat us of txbn data, and the transmit shift register data flag, which indi cates whether transmission is in progress. (4) reception control parity check the receive operation is controlled according to the c ontents set in the asimn register. a check for parity errors is also performed during a receive operation, and if an error is detected, a value corresponding to the error contents is set in the asisn register. (5) receive shift register this is a shift register that converts the serial data that was input to the rxdn pin into parallel data. one byte of data is received, and if a stop bit is detected, the receive data is tr ansferred to receive buffer register n (rxbn). this register cannot be directly manipulated. (6) receive buffer register n (rxbn) rxbn is an 8-bit buffer register for holding receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, receive data is tr ansferred from the receive shift register to rxbn, synchronized with the end of the sh ift-in processing of one frame. also, the reception completi on interrupt request (intsrn) is generat ed by the transfer of data to rxbn. (7) transmit shift register this is a shift register that converts the parallel data that was transferred from transmit buffer register n (txbn) into serial data. when one byte of data is transferred from txbn, the sh ift register data is output from the txdn pin. this register cannot be directly manipulated. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 302 (8) transmit buffer register n (txbn) txbn is an 8-bit buffer for transmit data. a transmit oper ation is started by writing transmit data to txbn. the transmission completion interrupt request (intstn) is generated synchronized with the completion of transmission of one frame. (9) addition of transmission control parity a transmit operation is controlled by adding a start bit, parit y bit, or stop bit to the data that is written to the txbn register, according to the contents that were set in the asimn register. figure 13-2. block diagram of asynchronous serial interface n parity framing overrun internal bus asynchronous serial interface mode register n (asimn) receive buffer register n (rxbn) receive shift register reception control parity check transmit buffer register n (txbn) transmit shift register addition of transmission control parity brgn intsren intsrn intstn rxdn txdn remark n = 0, 1 chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 303 13.3 control registers (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register t hat controls the uartn transfer operation. this register can be read or written in 8-bit or 1-bit units. this register is set to 01h after reset. caution when using uartn, be sure to set the external pins related to uartn functions to the control mode before setting clock select register n (cksrn) and baud ra te generator control register n (brgcn), and then set the uartcaen bit to 1. then set the other bits. (1/3) <7> uartcaen asimn (n = 0, 1) <6> txen <5> rxen 4 psn1 3 psn0 2 cln 1 sln 0 isrmn after reset: 01h r/w address: asim0 fffffa00h, asim1 fffffa10h uartcaen controls the operating clock 0 stops clock supply to uartn. 1 supplies clock to uartn. ? if uartcaen = 0, uartn is asynchronously reset. ? if uartcaen = 0, uartn is reset. to operate uartn, first set uartcaen to 1. ? if the uartcaen bit is changed from 1 to 0, all the registers of uartn are initialized. to set uartcaen to 1 again, be sure to re-set the registers of uartn. ? the output of the txdn pin goes high when transmission is disabled, regardless of the setting of the uartcaen bit. txen enables/disables transmission 0 disables transmission 1 enables transmission ? set the txen bit to 1 after setting the uartcaen bit to 1 at startup. set the uartcaen bit to 0 after setting the txen bit to 0 to stop. ? to initialize the transmission unit, clear (0) the txen bit, and after letting 2 clock cycles (base clock) elapse, set (1) the txen bit again. if the txen bit is not set again, initialization may not be successful. (for details of the base clock, refer to 13.6 (1) (a) base clock (clock) .) chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 304 (2/3) rxen enables/disables reception 0 disables reception 1 enables reception ? set the rxen bit to 1 after setting the uartcaen bit to 1 at startup. set the uartcaen bit to 0 after setting the rxen bit to 0 to stop. ? to initialize the reception unit status, clear (0) the rxen bit, and after letting 2 clock cycles (base clock) elapse, set (1) the rxen bit again. if the rxen bit is not set again, initialization may not be succ essful. (for details of the base clock, refer to 13.6 (1) (a) base clock (clock) .) psn1 psn0 transmit operation receive operation 0 0 parity bit not output receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity ? to overwrite the ps1 and ps0 bits, first clear (0) the txen and rxen bits. ? if ?0 parity? is selected for reception, no parity judgment is performed. therefore, no error interrupt is generated because the pe bit of the asisn register is not set. remarks 1. when reception is disabled, the receive shift regi ster does not detect a start bit. no shift-in processing or transfer processing to receive buffer register n (rxbn) is performed, and the contents of the rxbn register are retained. when reception is enabled, the receive shift operation starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the rxbn register. a reception completion interrupt (intsrn) is also generated in synchronization with the transfer to the rxbn register. 2. (even parity) if the transmit data contains an odd number of bits with the value ?1?, the parity bit is set (1). if it contains an even number of bits with the value ?1?, the parity bit is cleared (0). this controls the number of bits with the value ?1? contained in the transmit data and t he parity bit so that it is an even number. during reception, the number of bits with the value ?1? contained in the receive data and the parity bit is counted, and if the number is odd, a parity error is generated. (odd parity) in contrast to even parity, odd par ity controls the number of bits with the value ?1? contained in the transmit data and the parity bit so that it is an odd number. during reception, the number of bits with the value ?1? contained in the receive data and the parity bit is counted, and if the number is even, a parity error is generated. (0 parity) during transmission, the parity bit is cleared (0) regardless of the transmit data. during reception, no parity error is generated because no parity bit is checked. (no parity) no parity bit is added to transmit data. during reception, the receive data is considered to have no parity bit. no parity error is generated because there is no parity bit. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 305 (3/3) cln specifies character length of 1 frame of transmit/receive data 0 7 bits 1 8 bits ? to overwrite the cl bit, first clear (0) the txen and rxen bits. sln specifies stop bit length of transmit data 0 1 bit 1 2 bits ? to overwrite the sl bit, first clear (0) the txen bit. ? since reception is always performed with a stop bit length of 1, the sl bit setting does not affect receive operations. isrmn enables/disables generation of reception completion interrupt requests when an error occurs 0 generate a reception error interrupt request (intsren) as an interrupt when an error occurs. in this case, no reception completion interrupt request (intsrn) is generated. 1 generate a reception completion interrupt request (intsrn) as an interrupt when an error occurs. in this case, no reception error interrupt request (intsren) is generated. ? to overwrite the isrm bit, first clear (0) the rxen bit. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 306 (2) asynchronous serial interfa ce status register n (asisn) the asisn register, which consists of 3 error flag bits (pen, fen and oven), indicates the error status when uartn reception is complete. the status flag, which indicates a reception error, alwa ys indicates the status of t he error that occurred most recently. that is, if the same error occurred several times before the receive data was read, this flag would hold only the status of the error that occurred last. the asisn register is cleared to 00h by a read oper ation. when a reception error occurs, receive buffer register n (rxbn) should be read and the error flag sh ould be cleared after the asisn register is read. this register is read-only, in 8-bit units. this register is cleared to 00h after reset. caution when the uartcaen bit or r xen bit of the asimn register is set to 0, or when the asisn register is read, the pen, fen, and oven bi ts of the asisn register are cleared (0). 7 0 asisn (n = 0, 1) 6 0 5 0 4 0 3 0 2 pen 1 fen 0 oven after reset: 00h r address: asis0 fffffa03h, asis1 fffffa13h pen status flag that indicates a parity error 0 when the asimn register?s uartcaen and rxen bits are both set to 0, or when the asisn register has been read 1 when reception was completed, the transmit data parity did not match the parity bit ? the operation of the pen bit differs acco rding to the settings of the ps1 and ps0 bits of the asimn register. fen status flag that indicates a framing error 0 when the asimn register?s uartcaen and rxen bits are both set to 0, or when the asisn register has been read 1 when reception was completed, no stop bit was detected ? for receive data stop bits, only the first bit is checked regardless of the stop bit length. oven status flag that indicates an overrun error 0 when the asimn register?s uartcaen and rxen bits are both 0, or when the asisn register has been read. 1 uartn completed the next receive operation before reading the rxbn receive data. ? when an overrun error occurs, the next receive data value is not written to the rxbn register and the data is discarded. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 307 (3) asynchronous serial interface tran smission status register n (asifn) the asifn register, which consists of 2 status flag bits, indicates the status during transmission. by writing the next data to the txbn register after data is transferred from the txbn register to the transmit shift register, transmit operations can be performed c ontinuously without suspension even during an interrupt interval. when transmission is performed continuously, da ta should be written after referencing the txbfn bit of the asifn register to prevent writi ng to the txbn register by mistake. this register is read-only, in 8-bit or 1-bit units. this register is cleared to 00h after reset. 7 0 asifn (n = 0, 1) 6 0 5 0 4 0 3 0 2 0 <1> txbfn <0> txsfn after reset: 00h r address: asif0 fffffa05h, asif1 fffffa15h txbfn transmit buffer data flag 0 data to be transferred next to the txbn register does not exist (when the asimn register?s powern or txen bit is 0, or when data has been transferred to the transmit shift register) 1 data to be transferred next exists in the txbn register (data exists in the txbn register when the txbn register has been written to) ? when transmission is performed contin uously, data should be written to the txbn register after confirming that this flag is 0. if writing to the txbn register is performed when this flag is 1, transmit data cannot be guaranteed. txsfn transmit shift register data flag (indicating the transmission status of uartn) 0 initial status or a waiting transmission (when the asimn register?s uartcaen or txen bit is set to 0, or following transfer completion, the next data transfer from the txbn register is not performed) 1 transmission in progress (when data has been transferred from the txbn register) ? when the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 follo wing the occurrence of a transmission completion interrupt. if initialization is performed when this flag is 1, transmit data cannot be guaranteed. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 308 (4) receive buffer register n (rxbn) the rxbn register is an 8-bit buffer register for stor ing parallel data that had been converted by the receive shift register. when reception is enabled (rxen bit = 1 in the asimn r egister), receive data is tr ansferred from the receive shift register to the rxbn register, synchronized with the completion of the shift-in processing of one frame. also, a reception completion interrupt request (intsrn) is generated by the transfer to the rxbn register. for information about the timing for generat ing this interrupt request, refer to 13.5 (4) receive operation . if reception is disabled (rxen bit = 0 in the asimn regist er), the contents of the r xbn register are retained, and no processing is performed for transferring data to th e rxbn register even when the shift-in processing of one frame is completed. also, no recept ion completion interrupt is generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxbn register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overr un error (oven) occurs, the receive data at that time is not transferred to the rxbn register. except when a reset is input, the rxbn register becomes ffh even when uartcaen = 0 in the asimn register. this register is read-only, in 8-bit units. this register is se t to ffh after reset. 7 rxbn7 rxbn (n = 0, 1) 6 rxbn6 5 rxbn5 4 rxbn4 3 rxbn3 2 rxbn2 1 rxbn1 0 rxbn0 after reset: ffh r address: rxb0 fffffa02h, rxb1 fffffa12h chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 309 (5) transmit buffer register n (txbn) the txbn register is an 8-bit buffe r register for setting transmit data. when transmission is enabled (txen bit = 1 in the asimn register), the transmit operat ion is started by writing data to txbn register. when transmission is disabled (txen bit = 0 in the asimn r egister), even if data is written to txbn register, the value is ignored. the txbn register data is transferred to the transmit shift register, and a transmission completion interrupt request (intstn) is generated, synchr onized with the completion of the transmission of one frame from the transmit shift register. for information about the timi ng for generating this interrupt request, refer to 13.5 (2) transmit operation . when txbfn bit = 1 in the asifn register, the txbn register must not be written. this register can be read or written in 8-bit units. this register is se t to ffh after reset. 7 txbn7 txbn (n = 0, 1) 6 txbn6 5 txbn5 4 txbn4 3 txbn3 2 txbn2 1 txbn1 0 txbn0 after reset: ffh r/w address: txb0 fffffa04h, txb1 fffffa14h chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 310 13.4 interrupt requests the following three types of interrupt requests are generated from uartn. ? reception error interrupt (intsren) ? reception completion interrupt (intsrn) ? transmission completion interrupt (intstn) the default priorities among these three types of interrupt requests is, from hi gh to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt. table 13-1. generated interrupts and default priorities interrupt priority reception error 1 reception completion 2 transmission completion 3 (1) reception error interrupt (intsren) when reception is enabled, a reception error interrupt is generated according to the logical or of the three types of reception errors explained for the asisn regist er. whether a reception erro r interrupt (intsren) or a reception completion interrupt (intsrn) is generated when an error occurs can be specified using the isrmn bit of the asimn register. when reception is disabled, no rec eption error interrupt is generated. (2) reception completion interrupt (intsrn) when reception is enabled, a reception completion interrupt is generated when data is shifted in to the receive shift register and transferred to the receive buffer register (rxbn). a reception completion interrupt request can be specified to be generated in place of a reception error interrupt using the isrmn bit of the asimn register even when a reception error has occurred. when reception is disabled, no reception completion interrupt is generated. (3) transmission completion interrupt (intstn) a transmission completion interrupt is generated when on e frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 311 13.5 operation (1) data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consis ts of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 13-3. the character bit length within one data frame, the ty pe of parity, and the stop bit length are specified by asynchronous serial interface mode register n (asimn). also, data is transferred lsb first. figure 13-3. asynchronous serial interface transmit/receive data format 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit .............. 1 bit ? character bits .... 7 bits or 8 bits ? parity bit ............ even parity, odd parity, 0 parity, or no parity ? stop bits ............ 1 bit or 2 bits chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 312 (2) transmit operation when the uartcaen bit is set to 1 in the asimn regi ster, a high level is output from the txdn pin. then, when the txen bit is set to 1 in the asimn regi ster, transmission is enabled, and the transmit operation is started by writing transmit data to transmit buffer register n (txbn). (a) transmission enabled state this state is set by the txen bit in the asimn register. ? txen = 1: transmission enabled state ? txen = 0: transmission disabled state since uartn does not have a cts (transmission enab led signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (b) starting a transmit operation in the transmission enabled state, a transmit operation is started by writing transmit data to transmit buffer register n (txbn). when a transmit operation is started, t he data in txbn is transferred to the transmit shift register. then, the transmit shift register outputs data to the txdn pin (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically. (c) transmission interrupt request when the transmit shift register becomes empty, a transmission completion interrupt request (intstn) is generated. the timing for generating the intstn interrupt differs according to the specification of the stop bit length. the intstn interrupt is generated at the same time that the last stop bit is output. if the data to be transmitted next has not been written to the txbn register, t he transmit operation is suspended. caution normally, when the transmit shift regi ster becomes empty, a transmission completion interrupt (intstn) is generated. ho wever, no transmission completion interrupt (intstn) is generated if the transmit sh ift register becomes empty due to reset. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 313 figure 13-4. asynchronous serial interface transmission completi on interrupt timing start stop d0 d1 d2 d6 d7 parity parity txdn (output) intstn (output) start d0 d1 d2 d6 d7 txdn (output) intstn (output) (a) stop bit length: 1 (b) stop bit length: 2 stop chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 314 (3) continuous transmission operation uartn can write the next transmit data to the txbn register at the timing t hat the transmit shift register starts the shift operation. this enables an efficient transmissi on rate to be realized by continuously transmitting data even during the intstn interrupt servicing after the transmission of one data frame. in addition, reading the txsfn bit of the asifn register afte r the occurrence of a transmission completion interrupt enables the txbn register to be efficiently written twice (2 bytes) without waiting for the trans mission of 1 data frame. when continuous transmission is performed, data should be written after referencing the asifn register to confirm the transmission status and whether or not data can be written to the txbn register. txbfn whether or not writing to txbn register is enabled 0 writing is enabled 1 writing is not enabled caution when transmission is perfo rmed continuously, write the first tr ansmit data (first byte) to the txbn register and confirm that the txbfn bit is 0, and then write the next transmit data (second byte) to txbn register. if writing to the txbn register is pe rformed when the txbfn bit is 1, transmit data cannot be guaranteed. while transmission is being performed continuously, whethe r writing to the txbn register later is enabled can be judged by confirming the txsfn bit after the occurrence of a transmission completion interrupt. txsfn transmission status 0 transmission is completed. however, the cautions concerning the txbfn bit must be observed. writing transmit dat a can be performed twice (2 bytes). 1 under transmission. transmit data can be written once (1 byte). cautions 1. when initializing th e transmission unit when continu ous transmission is completed, confirm that the txbfn bit is 0 after the occurrence of the tran smission completion interrupt, and then execute initialization. if initialization is perfor med when the txbfn bit is 1, transmit data cannot be guaranteed. 2. while transmission is bein g performed continuously, an o verrun error may occur if the next transmission is completed before th e intstn interrupt servicing following the transmission of 1 data frame is executed. an overrun error can be detected by embedding a program that can count the numbe r of transmit data and referencing the txsfn bit. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 315 figure 13-5. continuous transmission processing flow set registers interrupt occurrence wait for interrupt required number of transfers performed? write transmit data to txbn register write transmit data to txbn register when reading asifn register, txbfn = 0? when reading asifn register, txsfn = 1? when reading asifn register, txsfn = 0? no no no no yes yes yes yes end of transmission processing chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 316 (a) starting procedure the procedure to start continuous transmission is shown below. figure 13-6. continuous transmission starting procedure txdn (output) data (1) data (2) <5> <1> <2> <4> intstn (output) txbn register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asifn register (txbfn, txsfn bits) 00 10 11 01 01 11 01 11 txsn register start bit stop bit stop bit start bit note note since this period is a transition period from 10 to 01, when reading the txbf n and txsfn bits of the asifn register simultaneously, 11 or 00 may be read. thus, whether writing to the txbn register is enabled or not should be judged only for the txbfn bit. asifn register transmission starting procedure internal operation txbfn txsfn ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 1 0 <2> generate start bit ? read asifn register (confirm that txbfn bit = 0) start data (1) transmission 1 0 0 0 1/0 note 1/0 note 1 1 ? write data (2) < chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 317 (b) ending procedure the procedure for ending continuous transmission is shown below. figure 13-7. continuous transmission end procedure txdn (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intstn (output) txbn register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asifn register (txbfn, txsfn bits) uartcaen bit or txen bit 11 01 11 01 00 txsn register start bit start bit stop bit stop bit asifn register transmission end procedure internal operation txbfn txsfn <6> transmission of data (m ? 2) is in progress 1 1 <7> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (m) <8> generate start bit start data (m ? 1) transmission < chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 318 (4) receive operation the awaiting reception state is set by setting the uartcaen bit to 1 in the asimn register and then setting the rxen bit to 1 in the asimn register. to start the rece ive operation, first perform start bit detection. the start bit is detected by sampling the rxdn pin. when the receive operation begins, serial data is stored sequentially in the receive shift register according to the baud rate that was set. a reception completion interrupt (intsrn) is generated each ti me the reception of one frame of data is completed. normally, the receive data is transferred from receive buffer register n (rxbn) to memory by th is interrupt servicing. (a) reception enabled state the receive operation is set to the reception enabled st ate by setting the rxen bit in the asimn register to 1. ? rxen bit = 1: reception enabled state ? rxen bit = 0: reception disabled state in reception disabled state, the recept ion hardware stands by in the initia l state. at this time, the contents of receive buffer register n (rxbn) are retained, and no reception completion interrupt or reception error interrupt is generated. (b) starting a receive operation a receive operation is started by the detection of a start bit. the rxdn pin is sampled using the serial clock from baud rate generator n (brgn). (c) reception completion interrupt when rxen = 1 in the asimn register and the recepti on of one frame of data is completed (the stop bit is detected), a reception completion inte rrupt (intsrn) is generated and th e receive data within the receive shift register is transferred to rxbn at the same time. also, if an overrun error (oven) occurs, the receive dat a at that time is not transferred to receive buffer register n (rxbn), and either a reception completion interrupt (intsrn) or a reception error interrupt (intsren) is generated (the receive data within the receive shift register is transferred to rxbn) according to the isrmn bit setting in the asimn register. even if a parity error (pen) or framing error (fen ) occurs during a reception operation, the receive operation continues until stop bit is received, and a fter reception is completed, either a reception completion interrupt (intsrn) or a reception error in terrupt (intsren) is generated according to the isrm bit setting in the asimn register. if the rxen bit is reset (0) during a receive operation, the receive operation is immediately stopped. the contents of receive buffer register n (rxbn) and of th e asynchronous serial interface status register (asisn) at this time do not change, and no reception completion inte rrupt (intsrn) or reception error interrupt (intsren) is generated. no reception completion interrupt is generated when rxen = 0 (reception is disabled). chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 319 figure 13-8. asynchronous serial interf ace reception completion interrupt timing start d0 d1 d2 d6 d7 rxdn (input) intsrn (output) rxbn register parity stop cautions 1. be sure to read recei ve buffer register n (rxbn) even wh en a reception error occurs. if rxbn is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely. 2. reception is always performed assuming a stop bit length of 1. a second stop bit is ignored. (5) reception error the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. as a result of data reception, the various flags of the asisn register are set (1), and a reception error interrupt (intsren) or a recept ion completion interrupt (intsrn) is generated at the same time. the isrmn bit of the asimn register specifies whether intsren or intsrn is generated. the type of error that occurred during reception can be detected by reading the conten ts of the asisn register during the intsren or intsrn interrupt servicing. the contents of the asisn r egister are reset (0) by reading the asisn register. table 13-2. reception error causes error flag reception error cause pen parity error the parity specificat ion during transmission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from receive buffer register n (rxbn) chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 320 (a) separation of rece ption error interrupt a reception error interrupt can be separated from the intsrn interrupt and generated as the intsren interrupt by clearing the isrmn bi t of the asimn register to 0. figure 13-9. when reception error interrupt is se parated from reception completion interrupt (intsrn) (isrmn bit = 0) (a) no error occurs during reception (b) an error occurs during reception intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsrn does not occur figure 13-10. when reception erro r interrupt is included in reception completion interrupt (intsrn) (isrmn bit = 1) (a) no error occurs during reception (b) an error occurs during reception intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsren does not occur chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 321 (6) parity types and co rresponding operation a parity bit is used to detect a bit error in communicati on data. normally, the same type of parity bit is used on the transmission and reception sides. (a) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the rece ive data including the parity bit is counted, and a parity error is generated if this number is odd. (b) odd parity (i) during transmission in contrast to even parity, the parit y bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the rece ive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (d) no parity no parity bit is added to the transmit data. during reception, the receive operati on is performed as if there were no parity bit. since there is no parity bit, no parity error is generated. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 322 (7) receive data noise filter the rxdn signal is sampled at the rising edge of the prescaler output base clock (clock). if the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see figure 13-12 ). refer to 13.6 (1) (a) base clock (clock) regarding the base clock. also, since the circuit is configured as shown in figure 13 -11, internal processing during a receive operation is delayed by up to 2 clocks accordin g to the external signal status. figure 13-11. noise filter circuit rxdn q clock in ld_en q in internal signal a internal signal b match detector figure 13-12. timing of rx dn signal judged as noise internal signal a clock rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 323 13.6 dedicated baud rate generator n (brgn) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by uartn. the dedicated baud ra te generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. (1) baud rate generator n (brgn) configuration figure 13-13. configuration of baud rate generator n (brgn) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 tom output clock (f cksr ) selector uartcaen 8-bit counter match detector baud rate brgcn: mdln7 to mdln0 1/2 uartcaen and txen (or rxen) cksrn: tpsn3 to tpsn0 f xx remark f xx : main clock n = 0, 1 m = 4, 5 (m = 4 when n = 0, m = 5 when n = 1) (a) base clock (clock) when the uartcaen bit = 1 in the asimn register, the clock selected according to the tpsn3 to tpsn0 bits of the cksrn register is supplied to the transmission/reception unit. this clock is called the base clock (clock), and its frequency is referred to as f cksr . when uartcaen = 0, clock is fixed to low level. chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 324 (2) serial clock generation a serial clock can be generated according to the settings of the cksrn and brgcn registers. the base clock to the 8-bit counter is selected by the tpsn3 to tpsn0 bits of the cksrn register. the 8-bit counter divisor value can be set by the mdln7 to mdln0 bits of the brgcn register. (a) clock select register n (cksrn) the cksrn register is an 8-bit register for selecting the basic block using the t psn3 to tpsn0 bits. the clock selected by the tpsn3 to tpsn0 bits becomes the base clock (clock) of the transmission/reception module. its frequency is referred to as f cksr . this register can be read or written in 8-bit units. this register is cleared to 00h after reset. caution set the uartcaen bit of the asimn register to 0 before rewriting the tpsn3 to tpsn0 bits. 7 0 cksrn 6 0 5 0 4 0 3 tpsn3 2 tpsn2 1 tpsn1 0 tpsn0 after reset: 00h r/w address: cksr0 fffffa06h, cksr1 fffffa16h tpsn3 tpsn2 tpsn1 tpsn0 receive operation 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1,024 1 0 1 1 tom output other than above setting prohibited remark n = 0, 1 m = 4, 5 (m = 4 when n = 0, m = 5 when n = 1) chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 325 (b) baud rate generator c ontrol register n (brgcn) the brgcn register is an 8-bit regist er that controls the baud rate (serial transfer speed) of uartn. this register can be read or written in 8-bit units. this register is se t to ffh after reset. caution if the mdln7 to mdln0 bits are to be overwritten, the txen and rxen bits should be set to 0 in the asimn register first. 7 mdln7 brgcn (n = 0, 1) 6 mdln6 5 mdln5 4 mdln4 3 mdln3 2 mdln2 1 mdln1 0 mdln0 after reset: ffh r/w address: brgc0 fffffa07h, brgc1 fffffa17h md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 division value (k) serial clock 0 0 0 0 0 ? setting prohibited 0 0 0 0 1 0 0 0 8 f cksr /8 0 0 0 0 1 0 0 1 9 f cksr /9 0 0 0 0 1 0 1 0 10 f cksr /10 : : : : : : : : : : 1 1 1 1 1 0 1 0 250 f cksr /250 1 1 1 1 1 0 1 1 251 f cksr /251 1 1 1 1 1 1 0 0 252 f cksr /252 1 1 1 1 1 1 0 1 253 f cksr /253 1 1 1 1 1 1 1 0 254 f cksr /254 1 1 1 1 1 1 1 1 255 f cksr /255 remarks 1. f cksr : frequency [hz] of base clock (clock) selected by tpsn3 to tpsn0 bits of cksrn register 2. k: value set by mdln7 to mdln0 bits (k = 8, 9, 10, ..., 255) 3. the baud rate is the output clock fo r the 8-bit counter divided by 2 4. : don?t care chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 326 (c) baud rate the baud rate is the value obtained by the following formula. f cksr 2 k f cksr = frequency [hz] of base clock (clock) selected by tpsn3 to tpsn0 bits of cksrn register. k = value set by mdln7 to mdln0 bits of brgcn register (k = 8, 9, 10, ..., 255) (d) baud rate error the baud rate error is obtained by the following formula. [%] 100 1 rate) baud (normal rate baud desired error) with rate (baud rate baud actual (%) error ? = ? ? ? ? ? ? ? ? cautions 1. make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error duri ng reception is within the allowable baud rate range described in (4) allowable baud rate range dur ing reception. example base clock frequency = 20 mhz = 20,000,000 hz setting of mdln7 to mdln0 bits in brgc0 register = 01000001b (k = 65) target baud rate = 153,600 bps baud rate = 20m/(2 65) = 20,000,000/(2 65) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%] baud rate = [bps] chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 327 (3) baud rate setting example table 13-3. baud rate generator setting data f xx = 20 mhz f xx = 17 mhz f xx = 13.5 mhz f xx = 8 mhz baud rate [bps] f cksr k err f cksr k err f cksr k err f cksr k err 300 f xx /512 65 0.16 f xx /128 221 0.16 f xx /1024 22 ? 0.12 f xx /1024 13 0.16 600 f xx /256 65 0.16 f xx /64 221 0.16 f xx /1024 11 ? 0.12 f xx /512 13 0.16 1,200 f xx /128 65 0.16 f xx /32 221 0.16 f xx /512 11 ? 0.12 f xx /256 13 0.16 2,400 f xx /64 65 0.16 f xx /16 221 0.16 f xx /256 11 ? 0.12 f xx /128 13 0.16 4,800 f xx /32 65 0.16 f xx /8 221 0.16 f xx /128 11 ? 0.12 f xx /64 13 0.16 9,600 f xx /16 65 0.16 f xx /4 221 0.16 f xx /64 11 ? 0.12 f xx /32 13 0.16 19,200 f xx /8 65 0.16 f xx /2 221 0.16 f xx /32 11 ? 0.12 f xx /16 13 0.16 31,250 f xx /32 10 0.00 f xx /16 17 0.00 f xx /8 27 0.00 f xx /16 8 0.00 38,400 f xx /4 65 0.16 f xx 221 0.16 f xx /16 11 ? 0.12 f xx /8 13 0.16 76,800 f xx /2 65 0.16 f xx 111 ? 0.29 f xx /8 11 ? 0.12 f xx /4 13 0.16 153,600 f xx 65 0.16 f xx 55 0.62 f xx /4 11 ? 0.12 f xx /2 13 0.16 312,500 f xx /4 8 0.00 f xx 27 0.74 f xx /2 11 ? 1.82 f xx 13 ? 1.54 remark f xx : main clock frequency f cksr : base clock frequency k: setting values of mdln7 to mdln0 bits in brgcn register err: baud rate error [%] chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 328 (4) allowable baud rate range during reception the degree to which a discrepancy from the transmission de stination?s baud rate is allowed during reception is shown below. caution the equations desc ribed below should be used to set th e baud rate error during reception so that it always is within the allowable error range. figure 13-14. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 13-13, after the start bit is detected, the receive data latch timi ng is determined according to the counter that was set by the brgcn register. if all da ta up to the final data (stop bit) is in time for this latch timing, the data can be received normally. if this is applied to 11-bit reception, the following is theoretically true. fl = (brate) ?1 brate: uartn baud rate k: brgcn register setting value fl: 1-bit data length when the latch timing margin is 2 base clocks (clock) , the minimum allowable transfer rate (flmin) is as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 flmin + = ? ? = chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 329 therefore, the transfer destination?s maximum re ceivable baud rate (brmax) is as follows. brate 2 k 21 22k (flmin/11) brmax 1 + = = ? similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 flmax 11 10 ? = + ? = 11 fl k 20 2 k 21 flmax ? = therefore, the transfer destination?s minimum receivable baud rate (brmin) is as follows. brate 2 k 21 20k (flmax/11) brmin 1 ? = = ? the allowable baud rate error of uartn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 13-4. maximum and minimum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ?3.61% 20 +4.26% ?4.31% 50 +4.56% ?4.58% 100 +4.66% ?4.67% 255 +4.72% ?4.73% remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgcn setting value chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 330 (5) transfer rate durin g continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock (clock) longer than normal. however, on t he reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 13-15. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bi t length by flstp, and the base clock frequency by f cksr yields the following equation. flstp = fl + 2/f cksr therefore, the transfer rate during co ntinuous transmission is as follows. transfer rate = 11 fl + 2/f cksr chapter 13 asynchronous serial interface n (uartn) user?s manual u15905ej2v1ud 331 13.7 cautions cautions to be observed when using uartn are shown below. (1) when the supply of clocks to uartn is stopped (for ex ample, in idle or stop mode), operation stops with each register retaining the value it had immediately befo re the supply of clocks was stopped. the txdn pin output also holds and outputs the value it had immediat ely before the supply of clocks was stopped. however, operation is not guaranteed after the supply of clocks is restarted. therefore, after the supply of clocks is restarted, the circuits should be initialized by setting uartcaen = 0, rxen = 0, and txen = 0 in the asimn register. (2) when the uartcaen bit is set to 0, the uartn unit is asynchronously reset. the output of the txdn pin goes to high level. to operate the uartn unit, set the uartcaen bit to 1, and then set the other bits (txen bit = 1, rxen bit = 1). to stop the uartn unit, clear the txen and rxen bits to 0, and then clear the uartcaen bit to 0. (3) do not change the values of the following contro l registers when the txen bit or rxen bit is 1. ? psn1, psn0, cln, sln, and isrmn bits of asimn register ? brgcn register before changing the values of the above r egisters, clear the txen or rxen bit to 0. the operation when the above values are changed with the txen or rxen bit set to 1 is prohibited. (4) to initialize the transmission or reception status, time corresponding to two cycles of the source clock (f cksr ) is required after clearing the txen bit or rxen bit to 0. (5) to successively transmit data, confirm the value of t he txbfn bit and then write data to the txbn register. writing data to the txbn register is prohibited wh en the txbfn bit is 1 (write disabled state). (6) clear the uartcaen bit to 0 before rewriting the cksrn register. (7) always read the rxbn register, even when a reception error has occurred. unless read, the reception error status (oven bit = 1) continues indefinitely. (8) uartn has a 2-stage buffer configuration consisting of transmit buffer register n (txbn) and the transmit shift register, and has status flags (the txbf n and txsfn bits of the asifn registe r) that indicate the status of each buffer. if the txbfn and txsfn bits ar e read in continuous transmission, the value changes from 10 to 01, but since this change timing is in the period in which data is shifted from txbn to the transmit shift register, 11 or 00 may be read, depending on the timing. thus, read on ly the txbfn bit during continuous transmission. user?s manual u15905ej2v1ud 332 chapter 14 clocked serial interface n (csin) 14.1 features ? transfer rate: master mode: maximum 5 mbps slave mode: maximum 5 mbps ? half-duplex communications ? master mode and slave mode can be selected ? transmission data length: 8 bits ? transfer data direction can be switched between msb first and lsb first ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire method ? son: serial data output ? sin: serial data input ? sckn: serial clock input/output ? interrupt sources: 1 type ? transmission/reception completion interrupt (intcsin) ? transmission/reception mode or recept ion-only mode can be specified ? on-chip transmit buffer (sotbn) remark n = 0 to 3 (v850es/sa2) n = 0 to 4 (v850es/sa3) chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 333 14.1.1 switching modes between csi0 and i 2 c csi0 and i 2 c of the v850es/sa2 and v850es/sa3 share pins, and therefore these interfaces cannot be used at the same time. select csi0 or i 2 c in advance by using port mode control r egister 4 (pmc4) and port function control register 4 (pfc4) (refer to 4.3.4 port 4 ). cautions 1. csi0 or i 2 c transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. be sure to disable the operation of the unit that is not used. 2. i 2 c: pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only figure 14-1. selecting csi0 or i 2 c mode 7 0 pmc4 6 pmc46 5 pmc45 4 pmc44 3 pmc43 2 pmc42 1 pmc41 0 pmc40 7 0 pfc4 6 pfc46 5 0 4 pfc44 3 0 2 pfc42 1 pfc41 0 0 after reset: 00h r/w address: fffff448h after reset: 00h r/w address: fffff468h pmc4n pfc4n operation mode 0 port i/o mode 1 0 csi0 mode 1 1 i 2 c mode remarks 1. n = 1, 2 2. = don?t care chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 334 14.1.2 switching modes between csi1 and uart0 csi1 and uart0 of the v850es/sa2 and v850es/sa3 share pins, and therefore these interfaces cannot be used at the same time. select csi1 or uart0 in advance by us ing port mode control register 3 (pmc3) and port function control register 3 (pfc3) (refer to 4.3.3 port 3 ). caution csi1 or uart0 transmission/reception opera tions are not guaranteed if the mode is changed during transmission or reception. be sure to disable the operation of the unit that is not used. figure 14-2. selecting csi1 or uart0 mode 7 0 pmc3 6 0 5 0 4 0 3 0 2 pmc32 1 pmc31 0 pmc30 7 0 pfc3 6 0 5 0 4 0 3 0 2 0 1 pfc31 0 pfc30 after reset: 00h r/w address: fffff446h after reset: 00h r/w address: fffff466h pmc3n pfc3n operation mode 0 port i/o mode 1 0 csi1 mode 1 1 uart0 mode remarks 1. n = 0, 1 2. = don?t care 14.2 configuration csin is controlled by the clocked serial interface mode regi ster (csimn). transmit/receive data can be written to or read from the sion register. (1) clocked serial interface mode register n (csimn) the csimn register is an 8-bit register for specifying the operation of csin. (2) clocked serial interface cloc k selection register n (csicn) the csicn register is an 8-bit register fo r controlling the transmit operation of csin. (3) serial i/o shift register n (sion) the sion register is an 8-bit register for converting between serial data and parallel data. sion is used for both transmission and reception. data is shifted in (reception) or shifted out (transmissi on) beginning at either the msb side or the lsb side. actual transmit/receive operations are controlled by reading or writing sion. chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 335 (4) clocked serial interface transm it buffer register n (sotbn) the sotbn register is an 8-bit buffer register for storing transmit data. (5) selector the selector selects the serial clock to be used. (6) serial clock controller the serial clock controller co ntrols the supply of serial clocks to the shift register. when an internal clock is used, it also controls the clocks that are output to the sckn pin. (7) serial clock counter the serial clock counter counts serial clocks that ar e output or input during transmit and receive operations and checks that 8-bit data has been transmitted or received. (8) interrupt controller the interrupt controller controls whether or not an inte rrupt request is generated when the serial clock counter has counted eight serial clocks. figure 14-3. clocked seri al interface block diagram selector cksn0 to cksn2 intcsin csotn son transfer clock controller transfer mode controller transfer data controller transmit buffer (sotbn) selector son latch sin sckn shift register (sion) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 tom csien, trmdn, dirn, ckpn, dapn remarks 1. m = 2 when n = 0 m = 3 when n = 1 m = 4 when n = 2 m = 5 when n = 3 m = 5 when n = 4 (v850es/sa3 only) 2. f xx : main clock frequency chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 336 14.3 control registers (1) clocked serial interface mode register n (csimn) the csin register controls the operation of csin. this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. caution to use csin, be sure to se t the external pins related to the csin function to control mode and set the csicn register. then set the csien bit to 1 before setting the other bits. remark n = 0 to 3 (v850es/sa2) n = 0 to 4 (v850es/sa3) chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 337 csien csin operation is disabled (son = low level, sckn = high level) csin operation is enabled csien 0 1 csin operation enable/disable specification csimn trmdn 0 dirn 0 0 0 csotn note 2 after reset: 00h r/w address: csim0 fffffd00h, csim1 fffffd10h, csim2 fffffd20h csim3 fffffd30h, csim4 note 1 fffffd40h ? if csien is set to 0, the csin unit can be reset asynchronously. ? if csien = 0, the csin unit is in a reset state. therefore, to operate csin, csien must be set to 1. ? if the csien bit is changed from 1 to 0, all registers of the csin unit are initialized. to set csien to 1 again, the registers of the csin unit must be set again. reception-only mode transmission/reception mode trmdn 0 1 transmission mode specification ? if trmdn = 0, reception-only transfers are performed. in addition, the son pin output is fixed at low level. data reception is started by reading the sion register. if trmdn = 1, transmission/reception is started by writing data to the sotbn register. ? the trmdn bit can be overwritten only when csotn = 0. msb first lsb first dirn 0 1 transfer direction mode (msb/lsb specification) ? the dirn bit can be overwritten only when csotn = 0. idle status transfer execution status csotn note 2 0 1 transfer status display flag ? this flag is used to judge whether writing to the shift register (sion) is enabled or not when starting serial data transmission in transmission/reception mode (trmdn = 1) ? the csotn bit is reset when the csie bit is cleared (0). <7> <0> <6> < > notes 1. csim4: v850es/sa3 only 2. the csotn bit is read-only. caution be sure to set bits 5 and 3 to 1 to 0. remark n = 0 to 3 (v850es/sa2) n = 0 to 4 (v850es/sa3) chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 338 (2) clocked serial interface cloc k selection register n (csicn) the csicn register is an 8-bit register t hat controls the transmit operation of csin. this register can be read or written in 8-bit units. this register is cleared to 00h after reset. caution the csicn register can only be overwritten after csien is clear ed to 0 in the csimn register. 0 ckpn 0 0 1 1 specification of data transmission/reception timing for sckn csicn 0 dapn 0 1 0 1 0 ckpn dapn cksn2 cksn1 cksn0 after reset: 00h r/w address: csic0 fffffd01h, csic1 fffffd11h, csic2 fffffd21h csic3 fffffd31h, csic4 note 1 fffffd41h cksn2 0 0 0 0 1 1 1 1 cksn1 0 0 1 1 0 0 1 1 cksn0 0 1 0 1 0 1 0 1 input clock f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 tom output note 2 external clock (sckn) master mode master mode master mode master mode master mode master mode master mode slave mode mode d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) notes 1. csic4: v850es/sa3 only 2. m = 2 when n = 0 m = 3 when n = 1 m = 4 when n = 2 m = 5 when n = 3 m = 5 when n = 4 (v850es/sa3 only) caution set the input clock to 5 mhz or lower. chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 339 (a) transfer rate selection example baud rate (bps) cksn2 cksn1 cksn0 20 mhz operation 17 mhz operation 13.5 mhz operation 10 mhz operation 8 mhz operation 4 mhz operation 0 0 0 setting prohibited setting prohibited setting prohibited 5,000,000 4,000,000 2,000,000 0 0 1 5,000,000 4,250,000 3,375,000 2,500,000 2,000,000 1,000,000 0 1 0 2,500,000 2,125,000 1,687,500 1,250,000 1,000,000 500,000 0 1 1 1,250,000 1,062,500 843,750 625,000 500,000 250,000 1 0 0 625,000 531,250 421,875 312,500 250,000 125,000 1 0 1 312,500 265,625 210,938 156,250 125,000 62,500 chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 340 (3) serial i/o shift register n (sion) the sion register is an 8-bit shift register that converts parallel data to serial data. if trmdn = 0 in the csimn register, the transfer is started by reading sion. except when a reset is input, the sion register becomes 00h even when the csien bit of the csimn register is cleared (0). sion shifts data in (reception) or shifts data out (transmission) beginning at the msb or the lsb side. this register is read-only, in 8-bit units. caution the sion register can be accessed only when the system is in an idle state (csotn bit = 0 in the csimn register). sion7 sion sion6 sion5 sion4 sion3 sion2 sion1 sion0 after reset: 00h r address: sio0: fffffd02h, sio1: fffffd12h, sio2: fffffd22h sio3: fffffd32h, sio4 note : fffffd42h note sio4: v850es/sa3 only remark n = 0 to 3 (v850es/sa2) n = 0 to 4 (v850es/sa3) (4) receive-only serial i/o shift register n (sioen) the sioen register is an 8-bit shift r egister that converts parallel data into serial data. a receive operation does not start even if the sioe n register is read while the trmdn bit of t he csimn register is 0. therefore this register is used to read the value of the sion regist er (receive data) without st arting a receive operation. sioen shifts data in (reception) beg inning at the msb or the lsb side. except when a reset is input, the sioen register becomes 00h even when the csien bit of the csimn register is cleared (0). this register is read-only, in 8-bit units. caution the sioen register can be accessed only when the system is in an idle state (csotn bit = 0 in the csimn register). sioen7 sioen sioen6 sioen5 sioen4 sioen3 sioen2 sioen1 sioen0 after reset: 00h r address: sioe0: fffffd03h, sioe1: fffffd13h, sioe2: fffffd23h sioe3: fffffd33h, sioe4 note : fffffd43h note sioe4: v850es/sa3 only remark n = 0 to 3 (v850es/sa2) n = 0 to 4 (v850es/sa3) chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 341 (5) clocked serial interface transm it buffer register n (sotbn) the sotbn register is an 8-bit buffer register for storing transmit data. if transmission/reception mode is set (trmdn = 1 in the csimn register), a transmit operation is started by writing data to the sotbn register. this register can be read or written in 8-bit units. this register is cleared to 00h after reset. caution the sotbn register can be accessed only when the system is in an idle state (csotn bit = 0 in the csimn register). sotbn7 sotbn sotbn6 sotbn5 sotbn4 sotbn3 sotbn2 sotbn1 sotbn0 after reset: 00h r/w address: sotb0: fffffd04h, sotb1: fffffd14h, sotb2: fffffd24h sotb3: fffffd34h, sotb4 note : fffffd44h note sotb4: v850es/sa3 only remark n = 0 to 3 (v850es/sa2) n = 0 to 4 (v850es/sa3) chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 342 14.4 operation (1) transfer mode csin transmits and receives data using three lines: 1 clock line and 2 data lines. in reception-only mode (trmdn = 0 in the csimn register), the transfer is started by reading the sion register. to read the value of the sion register without starting reception, read the sioen register. in transmission/reception mode (trmdn = 1 in the csimn r egister), the transfer is started by writing data to the sotbn register. when an 8-bit transfer of csin ends, the csotn bit of the csimn register becomes 0, and transfer stops automatically. also, when the transfer ends, a trans mission/reception completion interrupt (intcsin) is generated. cautions 1. when csotn bit = 1 in the csimn regist er, the control registers and data registers should not be accessed. 2. if transmit data is writte n to the sotbn register and the trmdn bit of the csimn register is changed from 0 to 1, serial transfer is not performed. remark n = 0 to 3 (v850es/sa2) n = 0 to 4 (v850es/sa3) (2) serial clock (a) when internal clock is selected as the serial clock if reception or transmission is started, a serial clock is output from the sckn pi n, and the data of the sin pin is taken into the sion register sequentially or dat a is output to the son pin sequentially from the sion register when the data is synchronized with the serial clock in accordance with the setting of the ckpn and dapn bits of the csicn register. (b) when external clock is selected as the serial clock if reception or transmission is started, the data of the sin pin is taken into the sion register sequentially or output to the son pin sequentially in synchronization wit h the serial clock that has been input to the sckn pin following transmission/reception startup in accordance with the setting of the ckpn and dapn bits of the csicn register. if serial clock is input to the sckn pin when neither reception nor transmission is started, a shift operation will not be executed. remark n = 0 to 3 (v850es/sa2) n = 0 to 4 (v850es/sa3) chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 343 figure 14-4. transfer timing (a) when trmdn = 1, dirn = 0, ckpn = 0, and dapn = 0 10101010 1 0101010 (aah) (55h) (write 55h to sotbn) 55h (transmission data) csotn bit sckn reg-r/w sotbn sion sin son intcsin interrupt abh 56h adh b5h 6ah d5h aah 5ah remark n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) (b) when trmdn = 1, dirn = 0, ckpn = 0, and dapn = 1 10101010 1 0101010 (aah) (55h) (write 55h to sotbn) 55h (transmission data) csotn bit sckn reg-r/w sotbn sion sin son intcsin interrupt abh 56h adh b5h 6ah d5h aah 5ah remark n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 344 figure 14-5. clock timing (a) when ckpn = 0 and dapn = 0 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (b) when ckpn = 1 and dapn = 0 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (c) when ckpn = 0 and dapn = 1 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (d) when ckpn = 1 and dapn = 1 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 remark n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 345 14.5 output pins (1) sckn pin when csin operation is disabled (csien = 0) , the sckn pin output state is as follows. ckpn sckn pin output 0 fixed to high level 1 fixed to low level remarks 1. when the ckpn bit is overwritt en, the sckn pin output changes. 2. n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) (2) son pin when csin operation is disabled (csien = 0) , the son pin output state is as follows. trmdn dapn dirn son pin output 0 fixed to low level 0 son latch value (low level) 0 sotbn7 value 1 1 1 sotbn0 value remarks 1. if any of the trmdn, dapn, and dirn bits is overwritten, the son pin output changes. 2. n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) 3. : don?t care chapter 14 clocked serial interface n (csin) user?s manual u15905ej2v1ud 346 14.6 system configuration example csin performs 8-bit length data transfer using three signal lines: a serial clock (sckn), serial input (sin), and serial output (son). this is effective when connecting peripheral i/o that incor porate a conventional clocked serial interface, or a display controller to the v850es/sa2 or v850es/sa3 (n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3)). when connecting the v850es/sa2 or v850es/sa3 to several devices, lines for handshake are required. since the first communication bit can be selected as msb or lsb, communication with various devices can be achieved. figure 14-6. system configuration example of csi sck master cpu slave cpu (3-wire serial i/o 3-wire serial i/o) so si port (interrupt) port si so port port (interrupt) sck user?s manual u15905ej2v1ud 347 chapter 15 i 2 c bus to use the i 2 c bus function, set the p41/so0/sda and p42/ sck0/scl pins to n-ch open drain output. 15.1 features i 2 c has the following two modes. operation stopped mode i 2 c (inter ic) bus mode (multiple masters supported) (1) operation stopped mode this mode is used when serial transfers are not per formed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multiple masters supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock line (scl) and a serial data bus line (sda). this mode complies with the i 2 c bus format and the master device can output ?start condition?, ?data?, and ?stop condition? data to the slave device, via the serial data bus. the slave device automatically detects these received data by hardware. this function can simplify the part of application program that controls the i 2 c bus. since scl and sda are open-drain outputs, the i 2 c bus requires pull-up resistors for the serial clock line and the serial data bus line. caution follow the procedure below to set n-ch open drain. <1> set the p4n bit to 1. <2> set the pf4n bit to 1. <3> set the iice bit to 1. <4> set the pfc4n bit to 1. <5> set the pmc4n bit to 1. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 348 15.1.1 switching modes between i 2 c and csi0 csi0 and i 2 c of the v850es/sa2 and v850es/sa3 share pins, and therefore these interfaces cannot be used at the same time. select csi0 or i 2 c in advance by using port mode control r egister 4 (pmc4) and port function control register 4 (pfc4) (refer to 4.3.4 port 4 ). cautions 1. csi0 or i 2 c transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. be sure to disable the operation of the unit that is not used. 2. i 2 c: pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only figure 15-1. selecting csi0 or i 2 c mode 7 0 pmc4 6 pmc46 5 pmc45 4 pmc44 3 pmc43 2 pmc42 1 pmc41 0 pmc40 7 0 pfc4 6 pfc46 5 0 4 pfc44 3 0 2 pfc42 1 pfc41 0 0 after reset: 00h r/w address: fffff448h after reset: 00h r/w address: fffff468h pmc4n pfc4n operation mode 0 port i/o mode 1 0 csi0 mode 1 1 i 2 c mode remarks 1. n = 1, 2 2. = don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 349 figure 15-2. block diagram of i 2 c internal bus iic status register (iics) iic control register (iicc) slave address register (sva) noise eliminator noise eliminator match signal iic shift register (iic) so latch iice d q set clear cl1, cl0 sda scl n-ch open- drain output n-ch open drain output data hold time correction circuit ack output circuit wakeup controller ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic f xx tm4 output lrel wrel spie wtim acke stt spt msts ald exc coi trc ackd std spd start condition detector internal bus cld0 dad0 smc0 dfc0 cl01 cl00 clx iic clock selection register (iiccl) iic function expansion register (iicx) chapter 15 i 2 c bus user?s manual u15905ej2v1ud 350 a serial bus configuration example is shown below. figure 15-3. example of seri al bus configuration using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2 chapter 15 i 2 c bus user?s manual u15905ej2v1ud 351 15.2 configuration i 2 c includes the following hardware. table 15-1. configuration of i 2 c item configuration registers iic shift register (iic) slave address register (sva) control registers iic control register (iicc) iic status register (iics) iic clock selection register (iiccl) iic function expansion register (iicx) (1) iic shift register (iic) the iic register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8- bit serial data. the iic register can be used for both transmission and reception. write and read operations to the iic register are used to control the actual transmit and receive operations. the iic register can be read or written in 8-bit units. this register is cleared to 00h after reset. (2) slave address register (sva) the sva register sets local addresses when in slave mode. the sva register can be read or written in 8-bit units. this register is cleared to 00h after reset. (3) so latch the so latch is used to retain the sda pin?s output level. (4) wakeup controller this circuit generates an interrupt request when the ad dress received by this register matches the address value set to slave address register (sva) or when an extension code is received. (5) clock selector this selects the samp ling clock to be used. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 352 (6) serial clock counter this counter counts the serial clocks t hat are output and the serial clocks t hat are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic). an i 2 c interrupt is generated following either of two triggers. ? eighth or ninth clock of the serial clock (set by wtim bit note ) ? interrupt request generated when a stop co ndition is detected (set by spie bit note ) note wtim bit: bit 3 of iic control register (iicc) spie bit: bit 4 of iic control register (iicc) (8) serial clock controller in master mode, this circuit generates the clo ck output via the scl pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 353 15.3 control registers i 2 c is controlled by the following registers. iic control register (iicc) iic status register (iics) iic clock selection register (iiccl) iic function expansion register (iicx) the following registers are also used. iic shift register (iic) slave address register (sva) (1) iic control register (iicc) the iicc register is used to enable/disable i 2 c operations, set wait timing, and set other i 2 c operations. the iicc register can be read or wr itten in 8-bit or 1-bit units. this register is cleared to 00h after reset. caution when using the i 2 c bus mode, set the port in the contro l mode (refer to 15.1.1 switching modes between i 2 c and csi0). also set the n-ch open-drain output mode (refer to 4.3.4 (2) (e) port function register 4 (pf4)). chapter 15 i 2 c bus user?s manual u15905ej2v1ud 354 (1/4) iice condition for clearing (iice= 0) ? cleared by instruction ? after reset condition for setting (iice = 1) ? set by instruction iice 0 1 operation stopped. iic status register (iics) preset. internal operation stopped. operation enabled. i 2 c operation enable/disable specification iicc lrel wrel spie wtim acke stt spt after reset: 00h r/w address: fffffd82h condition for clearing (lrel = 0) note ? automatically cleared after execution ? after reset condition for setting (lrel = 1) ? set by instruction lrel 0 1 normal operation this exits from the current communication operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl and sda lines are set to high impedance. the following flags are cleared. ? std ? ackd ? trc ? coi ? exc ? msts ? stt ? spt the standby mode following exit from communications remains in effect until the following communication entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code reception occurs after the start condition. exit from communications <7> <6> note this flag?s signal is invalid when iice = 0. remark std: bit 1 of iic status register (iics) ackd: bit 2 of iic status register (iics) trc: bit 3 of iic status register (iics) coi: bit 4 of iic status register (iics) exc: bit 5 of iic status register (iics) msts: bit 7 of iic status register (iics) chapter 15 i 2 c bus user?s manual u15905ej2v1ud 355 (2/4) condition for clearing (wrel = 0) note ? automatically cleared after execution ? after reset condition for setting (wrel = 1) ? set by instruction wrel 0 1 wait not canceled wait canceled. this setting is automatically cleared after wait is canceled. wait cancellation control condition for clearing (spie = 0) note ? cleared by instruction ? after reset condition for setting (spie = 1) ? set by instruction spie 0 1 disabled enabled enable/disable generation of interrupt request when stop condition is detected condition for clearing (wtim = 0) note ? cleared by instruction ? after reset condition for setting (wtim = 1) ? set by instruction wtim 0 1 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for master device. interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for master device. control of wait and interrupt request generation this bit?s setting is invalid during an address transfer and is valid as the transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. note this flag?s signal is invalid when iice = 0. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 356 (3/4) condition for clearing (acke = 0)note ? cleared by instruction ? after reset condition for setting (acke = 1) ? set by instruction acke 0 1 acknowledgment disable. acknowledge control condition for clearing (stt = 0) ? cleared by instruction ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when lrel = 1 ? when iice = 0 ? after reset condition for setting (stt = 1) ? set by instruction stt 0 1 start condition trigger acknowledgment enabled. during the ninth clock period, the sda line is set to low level. however, ack is invalid during address transfers and is valid when exc = 1. start condition not generated. when bus is released (in stop mode): generates a start condition (for starting as master). the sda line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scl is changed to low level. when bus is not used: this trigger functions as a start condition reserve flag. when set, it releases the bus and then automatically generates a start condition. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set during transfer. can be set only when acke has been set to 0 and slave has been notified of final reception. ? for master transmission: a start condition cannot be generated normally during the ack period. set during the wait period. ? cannot be set at the same time as spt note this flag?s signal is invalid when iice = 0. remark bit 1 (stt) is 0 if it is read immediately after data setting. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 357 (4/4) condition for clearing (spt = 0) ? cleared by instruction ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when lrel = 1 ? when iice = 0 ? after reset condition for setting (spt = 1) ? set by instruction spt 0 1 stop condition trigger cautions concerning set timing ? for master reception: cannot be set during transfer. can be set only when acke has been set to 0 and during the wait period after slave has been notified of final reception. ? for master transmission: a stop condition cannot be generated normally during the ack period. set during the wait period. ? cannot be set at the same time as stt. ? spt can be set only when in master mode note . ? when wtim has been set to 0, if spt is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. when a ninth clock must be output, wtim should be changed from 0 to 1 during the wait period following output of eight clocks, and spt should be set during the wait period that follows output of the ninth clock. stop condition is not generated. stop condition is generated (termination of master device?s transfer). after the sda line goes to low level, either set the scl line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sda line is changed from low l evel to high level and a stop condition is generated. note set spt only in master mode. however, spt must be set and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see 15.14 cautions . caution when bit 3 (trc) of the iic status register ( iics) is set to 1, wrel is set during the ninth clock and wait is canceled, after which trc is cleared and the sda line is set to high impedance. remark bit 0 (spt) is 0 if it is read immediately after data setting. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 358 (2) iic status register (iics) the iics register is used to indicate the status of i 2 c. the iics register is read-only, in 8-bit or 1-bit units. this register is cleared to 00h after reset. (1/3) msts condition for clearing (msts = 0) ? when a stop condition is detected ? when ald = 1 ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? after reset condition for setting (msts = 1) ? when a start condition is generated msts 0 1 slave device status or communication standby status master device communication status master device status iics ald exc coi trc ackd std spd after reset: 00h r address: fffffd86h condition for clearing (ald = 0) ? automatically cleared after iics is read note ? when iice changes from 1 to 0 ? after reset condition for setting (ald = 1) ? when the arbitration result is a ?loss?. ald 0 1 this status means either that there was no arbitration or that the arbitration result was a ?win?. this status indicates the arbitration result was a ?loss?. msts is cleared. detection of arbitration loss condition for clearing (exc = 0) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? after reset exc 0 1 extension code was not received. extension code was received. detection of extension code reception condition for setting (exc = 1) ? when the higher four bits of the received address data is either ?0000? or ?1111? (set at the rising edge of the eighth clock). note this register is also cleared when a bit manipulati on instruction is executed for bits other than iics. remark lrel: bit 6 of iic control register (iicc) iice: bit 7 of iic control register (iicc) chapter 15 i 2 c bus user?s manual u15905ej2v1ud 359 (2/3) condition for clearing (coi = 0) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? after reset coi 0 1 addresses do not match. addresses match. detection of matching addresses trc 0 1 detection of transmit/receive status condition for clearing (trc = 0) ? when a stop condition is detected ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? cleared by wrel = 1 note ? when ald changes from 0 to 1 ? after reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication condition for setting (trc = 1) master ? when a start condition is generated slave ? when ?1? is input by the first byte?s lsb (transfer direction specification bit) condition for setting (coi = 1) ? when the received address matches the local address (sva) (set at the rising edge of the eighth clock). receive status (other than transmit status). the sda line is set to high impedance. transmit status. the value in the so latch is enabled for output to the sda line (valid starting at the falling edge of the first byte?s ninth clock). note trc is cleared and the sda line becomes high impedanc e when bit 5 (wrel) of the iic control register (iicc) is set and the wait state is released at ninth clock when bit 3 (trc) of the iic status register (iics) = 1. remark wrel: bit 5 of iic control register (iicc) lrel: bit 6 of iic control register (iicc) iice: bit 7 of iic control register (iicc) chapter 15 i 2 c bus user?s manual u15905ej2v1ud 360 (3/3) condition for clearing (ackd = 0) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? after reset ackd 0 1 ack was not detected. ack was detected. detection of ack std 0 1 detection of start condition spd 0 1 detection of stop condition condition for setting (ackd = 1) ? after the sda line is set to low level at the rising edge of the scl?s ninth clock start condition was not detected. start condition was detected. this indicates that the address transfer period is in effect condition for clearing (std = 0) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lrel = 1 ? when iice changes from 1 to 0 ? after reset condition for setting (std = 1) when a start condition is detected stop condition was not detected. stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spd = 0) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when iice changes from 1 to 0 ? after reset condition for setting (spd = 1) when a stop condition is detected remark lrel: bit 6 of iic control register (iicc) iice: bit 7 of iic control register (iicc) chapter 15 i 2 c bus user?s manual u15905ej2v1ud 361 (3) iic clock selection register (iiccl) the iiccl register is used to set the transfer clock for i 2 c. the iiccl register can be read or written in 8-bit or 1-bi t units. set the smc, cl1, and cl0 bits in combination with the clx bit of the iic functi on expansion register (iicx) (see table 15-2 transfer clock setting ). this register is cleared to 00h after reset. 0 condition for clearing (cld = 0) ? when the scl line is at low level ? when iice = 0 ? after reset condition for setting (cld = 1) ? when the scl0 line is at high level cld 0 1 scl line was detected at low level. scl line was detected at high level. detection of scl line level (valid only when iice = 1) iiccl 0 cld dad smc dfc cl1 cl0 after reset: 00h r/w note address: fffffd84h condition for clearing (dad = 0) ? when the sda line is at low level ? when iice = 0 ? after reset condition for setting (dad = 1) ? when the sda line is at high level dad 0 1 sda line was detected at low level. sda line was detected at high level. detection of sda line level (valid only when iice = 1) smc 0 1 operates in standard mode. operates in high-speed mode. operation mode switching the digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfc switching (on/off). dfc 0 1 digital filter off. digital filter on. digital filter operation control note bits 4 and 5 are read-only bits. remark iice: bit 7 of iic control register (iicc) chapter 15 i 2 c bus user?s manual u15905ej2v1ud 362 (4) iic function expansi on register (iicx) the iicx register is used to set the function expansion of i 2 c (valid only in high-speed mode). the iicx register can be read or written in 8-bit or 1- bit units. set the clx bit in combination with the smc, cl1, and cl0 bits of the iic cloc k selection register (iiccl) (see table 15-2 transfer clock setting ). this register is cleared to 00h after reset. iicx after reset: 00h r/w address: fffffd85h 0 0 0 0 0 0 0 clx (5) i 2 c transfer clock setting method the i 2 c transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 12, 18, 24, 48, 86, 88, 172 (see table 15-2 transfer clock setting .) t: 1/f xx t r : scl rise time t f : scl fall time for example, the i 2 c transfer clock frequency (f scl ) when f xx = 16 mhz, m = 172, t r = 200 ns, and t f = 50 ns is calculated using the following expression. f scl = 1/(172 62.5 ns + 200 ns + 50 ns) ? 90.9 khz figure 15-4. i 2 c transfer clock frequency (f scl ) m t + t r + t f m/2 t t f t r m/2 t scl scl inversion scl inversion scl inversion the transfer clock is set using a combination of the sm c, cl1, and cl0 bits of iic clock select register (iiccl), the clx bit of iic function expansion register (iicx). chapter 15 i 2 c bus user?s manual u15905ej2v1ud 363 table 15-2. transfer clock setting iicx iiccl bit 0 bit 3 bit1 bit0 clx smc cl1 cl0 transfer clock settable main clock frequency (f xx ) range operation mode 0 0 0 0 f xx /88 4.0 mhz to 8.38 mhz 0 0 0 1 f xx /172 8.38 mhz to 16.76 mhz 0 0 1 0 f xx /86 4.19 mhz to 8.38 mhz 0 0 1 1 to4 output/66 tm4 setting note normal mode (smc = 0) 0 1 0 f xx /48 8 mhz to 16.76 mhz 0 1 1 0 f xx /24 4 mhz to 8.38 mhz 0 1 1 1 to4 output/18 tm4 setting note high-speed mode (smc = 1) 1 0 setting prohibited 1 1 0 f xx /24 8.00 mhz to 8.38 mhz 1 1 1 0 f xx /12 4.00 mhz to 4.19 mhz normal mode (smc = 0) 1 1 1 1 setting prohibited remarks 1. : don?t care 2. when the transfer clock is set to timer output, the p96/to4/a6 pin does not need to be set in timer output mode. (6) iic shift register (iic) the iic register is used for serial transmission/recepti on (shift operations) that are synchronized with the serial clock. the iic register can be read or written in 8-bit units, but data should not be written to iic during a data transfer. this register is cleared to 00h after reset. iic after reset: 00h r/w address: fffffd80h (7) slave address register (sva) the sva register holds the i 2 c bus?s slave addresses. the sva register can be read or written in 8-bit units, but bit 0 is fixed to 0. this register is cleared to 00h after reset. 0 sva after reset: 00h r/w address: fffffd83h chapter 15 i 2 c bus user?s manual u15905ej2v1ud 364 15.4 i 2 c bus mode functions (1) pin configuration the serial clock pin (scl) and serial data bus pin (sda) are configured as follows. scl ..............this pi n is used for serial clock i/o. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. sda .............this pin is used for serial data i/o. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open- drain outputs, an external pull-up resistor is required. figure 15-5. pin configuration diagram v dd scl sda scl sda v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device chapter 15 i 2 c bus user?s manual u15905ej2v1ud 365 15.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start condition? , ?data?, and ?stop condition? output via the i 2 c bus?s serial data bus is shown below. figure 15-6. i 2 c bus serial data transfer timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 scl sda start condition address r/w ack data data stop condition ack ack the master device outputs the start condi tion, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl) is continuously output by the mast er device. however, in the slave device, scl?s low-level period can be extended and a wait can be inserted. (1) start condition a start condition is met when the scl pin is at high leve l and the sda pin changes from high level to low level. the start conditions for the scl pin and sda pin are sign als that the master device outputs to the slave device when starting a serial transfer. the slave device in cludes hardware for detecting start conditions. figure 15-7. start conditions h scl sda a start condition is output when bit 1 (s tt) of the iic control register (iicc) is set to 1 after a stop condition has been detected (spd: bit 0 = 1 in iic status register (iics)). when a start condition is detected, bit 1 (std) of iics is set to 1. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 366 (2) addresses the 7 bits of data that follow the star t condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit data matches the data values stored in slave address register (sva). if t he 7-bit data matches the sva register values, the slave device is sele cted and communicates with the mast er device until the master device transmits a start condition or stop condition. figure 15-8. address address scl 1 sda intiic note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note intiic is not generated if data other than a loca l address or extension code is received during slave device operation. the slave address and the eighth bit, which spec ifies the transfer direction as described in (3) transfer direction specification below, are written together to the iic shi ft register (iic) and are then output. received addresses are written to iic. the slave address is assigned to the higher 7 bits of the iic register. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 367 (3) transfer direction specification in addition to the 7-bit address data, the master device se nds 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direct ion specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 15-9. transfer direction specification scl 1 sda intiic 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note intiic is not generated if data other than a loca l address or extension code is received during slave device operation. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 368 (4) acknowledge signal (ack) the acknowledge signal (ack) is used by the transmi tting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as nor mal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop conditi on or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. <1> reception was not correctly performed. <2> the final data was received. when the receiving device sets the sda line to low leve l during the ninth clock, the ack signal becomes active (normal receive response). when bit 2 (acke) of the iic control register (iicc) is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following the 7 address data bits causes bit 3 (trc) of the iic status register (iics) to be set. when the trc bit?s value is 0, it indi cates receive mode. therefore, acke should be set to 1. when the slave device is receiving (when trc = 0), if the slave device does not need to receive any more data after receiving several bytes, setting acke to 0 will prevent the master devic e from starting transmission of the subsequent data. similarly, when the master device is receiving (when trc = 0) and the subsequent data is not needed and when either a restart condition or a stop condition shou ld therefore be output, setting acke to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sda line (i.e., stops transmission) during transmission from the slave device. figure 15-10. ack signal scl 1 sda 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack when the local address is received, an ack signal is automatically output in sync hronization with the falling edge of the eighth clock of scl regar dless of the acke bit value. no ack signal is output if the received address is not a local address. the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected: the ack signal is output at the falling edge of the eighth clock of scl if acke is set to 1 before wait cancellation. when 9-clock wait is selected: the ack signal is automat ically output at the falling edge of the eighth clock of scl if acke has already been set to 1. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 369 (5) stop condition when the scl pin is at high level, changing the sda pin from low level to high level generates a stop condition. a stop condition is a signal that t he master device outputs to the slave device when serial transfer has been completed. the slave device includes hardware that detects stop conditions. figure 15-11. stop condition h scl sda a stop condition is generated when bit 0 (spt) of the iic control register (iicc) is set to 1. when the stop condition is detected, bit 0 (spd) of the iic status regist er (iics) is set to 1 and intiic is generated when bit 4 (spie) of iicc is set to 1. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 370 (6) wait signal (wait) the wait signal (wait) is used to notify the communication part ner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl pin to low level notifies the communication partner of the wait stat us. when the wait status has been canceled for both the master and slav e devices, the next data transfer can begin. figure 15-12. wait signal (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and acke = 1) scl 6 sda 78 9 123 scl iic 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic scl acke master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iic data write (cancel wait) slave wait after output of eighth clock. ffh is written to iic or wrel is set to 1. transfer lines chapter 15 i 2 c bus user?s manual u15905ej2v1ud 371 figure 15-12. wait signal (2/2) (2) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acke = 1) scl 6 sda 789 123 scl iic 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic scl acke master master and slave both wait after output of ninth clock. iic data write (cancel wait) slave ffh is written to iic or wrel is set to 1. output according to previously set acke value transfer lines remark acke: bit 2 of iic control register (iicc) wrel: bit 5 of iic control register (iicc) a wait may be automatically generated depending on the setting of bit 3 (wtim) of the iic control register (iicc). normally, when bit 5 (wrel) of the iicc register is set to 1 or when ffh is written to t he iic shift register (iic), the wait status is canceled and the tr ansmitting side writes data to the iic r egister to cancel the wait status. the master device can also cancel the wait status via either of the following methods. by setting bit 1 (stt) of iicc to 1 by setting bit 0 (spt) of iicc to 1 chapter 15 i 2 c bus user?s manual u15905ej2v1ud 372 15.6 i 2 c interrupt request (intiic) the following shows the value of the iic status register ( iics) at the intiic interrupt request generation timing and at the intiic interrupt timing. (1) master device operation (a) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when wtim = 0 spt = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 10xxx110b 2: iics = 10xxx000b 3: iics = 10xxx000b (wtim = 0) 4: iics = 10xxxx00b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 spt = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 10xxx110b 2: iics = 10xxx100b 3: iics = 10xxxx00b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 373 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) <1> when wtim = 0 stt = 1 spt = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iics = 10xxx110b 2: iics = 10xxx000b (wtim = 1) 3: iics = 10xxxx00b (wtim = 0) 4: iics = 10xxx110b (wtim = 0) 5: iics = 10xxx000b (wtim = 1) 6: iics = 10xxxx00b ? 7: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 stt = 1 spt = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 10xxx110b 2: iics = 10xxxx00b 3: iics = 10xxx110b 4: iics = 10xxxx00b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 374 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtim = 0 spt = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 1010x110b 2: iics = 1010x000b 3: iics = 1010x000b (wtim = 1) 4: iics = 1010xx00b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 spt = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 1010x110b 2: iics = 1010x100b 3: iics = 1010xx00b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 375 (2) slave device operation (when receiving sl ave address data (matches with sva)) (a) start ~ address ~ data ~ data ~ stop <1> when wtim = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 0001x110b 2: iics = 0001x000b 3: iics = 0001x000b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 0001x110b 2: iics = 0001x100b 3: iics = 0001xx00b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 376 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim = 0 (after restart, matches with sva) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 0001x110b 2: iics = 0001x000b 3: iics = 0001x110b 4: iics = 0001x000b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, matches with sva) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 0001x110b 2: iics = 0001xx00b 3: iics = 0001x110b 4: iics = 0001xx00b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 377 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtim = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 0001x110b 2: iics = 0001x000b 3: iics = 0010x010b 4: iics = 0010x000b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iics = 0001x110b 2: iics = 0001xx00b 3: iics = 0010x010b 4: iics = 0010x110b 5: iics = 0010xx00b ? 6: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 378 (d) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim = 0 (after restart, does not match with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 0001x110b 2: iics = 0001x000b 3: iics = 00000x10b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, does not match with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 0001x110b 2: iics = 0001xx00b 3: iics = 00000x10b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 379 (3) slave device operation (whe n receiving extension code) (a) start ~ code ~ data ~ data ~ stop <1> when wtim = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 0010x010b 2: iics = 0010x000b 3: iics = 0010x000b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 0010x010b 2: iics = 0010x110b 3: iics = 0010x100b 4: iics = 0010xx00b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 380 (b) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtim = 0 (after restart, matches with sva) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 0010x010b 2: iics = 0010x000b 3: iics = 0001x110b 4: iics = 0001x000b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, matches with sva) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iics = 0010x010b 2: iics = 0010x110b 3: iics = 0010xx00b 4: iics = 0001x110b 5: iics = 0001xx00b ? 6: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 381 (c) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtim = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 0010x010b 2: iics = 0010x000b 3: iics = 0010x010b 4: iics = 0010x000b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iics = 0010x010b 2: iics = 0010x110b 3: iics = 0010xx00b 4: iics = 0010x010b 5: iics = 0010x110b 6: iics = 0010xx00b ? 7: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 382 (d) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtim = 0 (after restart, does not match with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 0010x010b 2: iics = 0010x000b 3: iics = 00000x10b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 (after restart, does not match with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 0010x010b 2: iics = 0010x110b 3: iics = 0010xx00b 4: iics = 00000x10b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 383 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? 1 ? 1: iics = 00000001b remark ? : generated only when spie = 1 (5) arbitration loss operation (operati on as slave after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data <1> when wtim = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 0101x110b (example: when ald is read during interrupt servicing) 2: iics = 0001x000b 3: iics = 0001x000b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 0101x110b (example: when ald is read during interrupt servicing) 2: iics = 0001x100b 3: iics = 0001xx00b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 384 (b) when arbitration loss occurs durin g transmission of extension code <1> when wtim = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 0110x010b (example: when ald is read during interrupt servicing) 2: iics = 0010x000b 3: iics = 0010x000b ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care <2> when wtim = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics = 0110x010b (example: when ald is read during interrupt servicing) 2: iics = 0010x110b 3: iics = 0010x100b 4: iics = 0010xx00b ? 5: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 385 (6) operation when arbitration loss occurs (no communication after arbitration loss) (a) when arbitration loss occurs durin g transmission of slave address data st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iics = 01000110b (example: when ald is read during interrupt servicing) ? 2: iics = 00000001b remark : always generated ? : generated only when spie = 1 (b) when arbitration loss occurs dur ing transmission of extension code st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iicsn = 0110x010b (example: when ald is read during interrupt servicing) iicc?s lrel is set to 1 via software ? 2: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 386 (c) when arbitration loss o ccurs during data transfer <1> when wtim = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iics = 10001110b 2: iics = 01000000b (example: when ald is read during interrupt servicing) ? 3: iics = 00000001b remark : always generated ? : generated only when spie = 1 <2> when wtim = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iics = 10001110b 2: iics = 01000100b (example: when ald is read during interrupt servicing) ? 3: iics = 00000001b remark : always generated ? : generated only when spie = 1 chapter 15 i 2 c bus user?s manual u15905ej2v1ud 387 (d) when loss occurs due to restar t condition during data transfer <1> not extension code (example: mismatches with sva) st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iics = 1000x110b 2: iics = 01000110b (example: when ald is read during interrupt servicing) ? 3: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care dn = d6 to d0 <2> extension code st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iics = 1000x110b 2: iics = 0110x010b (example: when ald is read during interrupt servicing) iicc?s lrel is set to 1 via software ? 3: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care dn = d6 to d0 chapter 15 i 2 c bus user?s manual u15905ej2v1ud 388 (e) when loss occurs due to stop condition during data transfer st ad6 to ad0 rw ak d7 to dn sp 1 ? 2 1: iics = 1000x110b ? 2: iics = 01000001b remark : always generated ? : generated only when spie = 1 x: don?t care dn = d6 to d0 (f) when arbitration loss occurs due to low-level data when attempting to generate a restart condition when wtim = 1 stt = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 1000x110b 2: iics = 1000xx00b 3: iics = 01000100b (example: when ald is read during interrupt servicing) ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 389 (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition when wtim = 1 stt = 1 st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iics = 1000x110b 2: iics = 1000xx00b ? 3: iics = 01000001b remark : always generated ? : generated only when spie = 1 x: don?t care (h) when arbitration loss occurs due to low-level data when attempti ng to generate a stop condition when wtim = 1 spt = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics = 1000x110b 2: iics = 1000xx00b 3: iics = 01000000b (example: when ald is read during interrupt servicing) ? 4: iics = 00000001b remark : always generated ? : generated only when spie = 1 x: don?t care chapter 15 i 2 c bus user?s manual u15905ej2v1ud 390 15.7 interrupt request (intiic) generation timing and wait control the setting of bit 3 (wtim) of the iic control register (iicc) determines the timing by which intiic is generated and the corresponding wait control, as shown below. table 15-3. intiic signal generation timing and wait control during slave device operation during master device operation wtim address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the address se t to slave address register (sva). at this point, ack is output regardless of the value set to bit 2 (acke) of the iicc register. for a slave device that has received an extension code, the intiic signal occurs at the falling edge of the eighth clock. 2. if the received address does not match the contents of slave address register (sva), neither the intiic signal nor a wait occurs. remark the numbers in the table indicate the number of the serial clock?s clock signals. interrupt requests and wait control are both synchronized with t he falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: the interrupt and wait timing are determined regardless of the wtim bit. ? master device operation: the interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim bit. (2) during data reception ? master/slave device operation: the interrupt and wa it timing are determined according to the wtim bit. (3) during data transmission ? master/slave device operation: the interrupt and wa it timing are determined according to the wtim bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting bit 5 (wrel) of the iic control register (iicc) to 1 ? by writing to the iic shift register (iic) ? by start condition setting (bit 1 (stt) of iic control register (iicc) = 1) ? by stop condition setting (bit 0 (spt) of iic control register (iicc) = 1) when an 8-clock wait has been selected (wtim = 0), the ou tput level of ack must be determined prior to wait cancellation. (5) stop condition detection intiic signal is generated when a stop condition is detected. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 391 15.8 address match detection method when in i 2 c bus mode, the master device can select a partic ular slave device by transmitting the corresponding slave address. address match detection is performed automatically by hard ware. an interrupt request (intiic) occurs when a local address has been set to the slave address register (sva) and when the address set to sva matches the slave address sent by the master device, or when an extension code has been received. 15.9 error detection in i 2 c bus mode, the status of the seri al data bus (sda) during data transmission is captured by the iic shift register (iic) of the transmitting device, so the iic data prior to transmission can be compared with the transmitted iic data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match. 15.10 extension code (1) when the higher 4 bits of the receive address are eit her 0000 or 1111, the extension code flag (exc) is set for extension code reception and an interrupt request (intiic ) is issued at the falling edge of the eighth clock. the local address stored in the slave addr ess register (sva) is not affected. (2) if 11110xx0 is set to sva by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the intiic signal occurs at the falling edge of the eighth clock. higher four bits of data match: exc = 1 note seven bits of data match: coi = 1 note note exc: bit 5 of iic status register (iics) coi: bit 4 of iic status register (iics) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set bit 6 (lrel) of the iic control register (iicc) to 1 and the cp u will enter the next communication wait state. table 15-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 cbus address 0000 010 address that is reserved for different bus format 1111 0xx 10-bit slave address specification chapter 15 i 2 c bus user?s manual u15905ej2v1ud 392 15.11 arbitration when several master devices simultaneo usly output a start condition (when stt is set to 1 before std is set to 1 note ), communication among the master dev ices is performed as the number of clocks is adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in ar bitration, an arbitration loss flag (ald ) in the iic status register (iics) is set via the timing by which the arbitration loss occurred, and the scl and sda lines are both set to high impedance, which releases the bus. the arbitration loss is detected based on the timing of th e next interrupt request (the eighth or ninth clock, when a stop condition is detected, et c.) and the ald = 1 setting that has been made by software. for details of interrupt request timing, see 15.6 i 2 c interrupt request (intiic) . note std: bit 1 of iic status register (iics) stt: bit 1 of iic control register (iicc) figure 15-13. arbitration timing example master 1 master 2 transfer lines scl sda scl sda scl sda master 1 loses arbitration hi-z hi-z chapter 15 i 2 c bus user?s manual u15905ej2v1ud 393 table 15-5. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data reception when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transf er when stop condition is output (when spie = 1) note 2 when data is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output a restart condition when stop condition is output (when spie = 1) note 2 when data is at low level while attempting to output a stop condition when scl is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when wtim (bit 3 of iic control register (iicc)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim = 0 and the extension code ?s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set spie = 1 for master device operation. remark spie: bit 5 of iic control register (iicc) chapter 15 i 2 c bus user?s manual u15905ej2v1ud 394 15.12 wakeup function the i 2 c bus slave function is a function that generates an interrupt request (intiic) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wakeup standby mode is se t. this wakeup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detecte d, bit 5 (spie) of the iic control regi ster (iicc) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 395 15.13 communication reservation to start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is re leased. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel) of the iic cont rol register (iicc) was set to ?1?). if bit 1 (stt) of iicc is set while the bus is not being used, a start condition is automatic ally generated and the wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is det ected), writing to the iic shift register (iic) causes the master?s address transfer to start. at this point, bit 4 (spie) of iicc should be set. when the stt bit has been set, the operation mode (as st art condition or as communication reservation) is determined according to the bus status. if the bus has been re leased ...................................................a start condition is generated if the bus has not been released (stand by mode) ...................c ommunication reservation to detect which operation mode has been determined for the stt bit, set the stt bit, wait for the wait period, then check the msts (bit 7 of iic status register (iics)). wait periods, which should be set via software, are listed in table 15-6. these wait periods can be set via the settings for bits 3, 1, and 0 (smc, cl1, and cl0) in the iic clock selection register (iiccl). table 15-6. wait periods smc cl1 cl0 wait period 0 0 0 26 clocks 0 0 1 46 clocks 0 1 0 92 clocks 0 1 1 37 clocks 1 0 0 1 0 1 16 clocks 1 1 0 32 clocks 1 1 1 13 clocks chapter 15 i 2 c bus user?s manual u15905ej2v1ud 396 the communication reservation timing is shown below. figure 15-14. communication reservation timing 2 1 3456 2 1 3456 789 scl sda program processing hardware processing write to iic set spd and intiic stt = 1 communication reservation set std output by master with bus access iic: iic shift register stt: bit 1 of iic control register (iicc) std: bit 1 of iic status register (iics) spd: bit 0 of iic status register (iics) communication reservations are accepted of the following timi ng. after bit 1 (std) of the iic status register (iics) is set to 1, a communication reservation can be made by setti ng bit 1 (stt) of the iic control register (iicc) to 1 before a stop condition is detected. figure 15-15. timing for accep ting communication reservations scl sda std spd standby mode chapter 15 i 2 c bus user?s manual u15905ej2v1ud 397 the communication reservation flow chart is illustrated below. figure 15-16. communication reservation flow chart di stt = 1 define communication reservation wait cancel communication reservation no yes iic h ei msts = 0? (communication reservation) note (generate start condition) ; sets stt flag (communication reservation). ; secures wait period set by software (see table 15-6 ). ; confirmation of communication reservation ; clear user flag. ; iic write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation operation executes a write to the iic shift register (iic) when a stop condition interrupt request occurs. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 398 15.14 cautions after a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first ge nerate a stop condition to re lease the bus, then perform master device communication. when using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. <1> set the iic clock selection register (iiccl). <2> set bit 7 (iice) of the iic control register (iicc). <3> set bit 0 of iicc. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 399 15.15 communication operations (1) master operations the following is a flow chart of the master operations. figure 15-17. master operation flow chart iiccl h select transfer clock. iicc h iice = spie = wtim = 1 spt = 1 start iic write transfer. start iic write transfer. wrel = 1 start reception. generate stop condition. (no slave with matching address) generate restart condition or stop condition. start data processing data processing acke = 0 no yes no no no no no no yes yes yes yes yes intiic = 1? wtim = 0 acke = 1 intiic = 1? transfer completed? intiic = 1? ackd = 1? trc = 1? intiic = 1? ackd = 1? ; stop condition detection ; initializes iicc register ; address transfer completion no (receive) yes (transmit) chapter 15 i 2 c bus user?s manual u15905ej2v1ud 400 (2) slave operation an example of slave operation is shown below. figure 15-18. slave operation flow chart iicc h iice = 1 wrel = 1 start reception. detect restart condition or stop condition. start acke = 0 data processing data processing lrel = 1 no yes no no no no no no no yes no yes yes yes yes yes yes wtim = 0 acke = 1 intiic = 1? yes communicate? transfer completed? intiic = 1? wtim = 1 start iic write transfer. intiic = 1? exc = 1? coi = 1? trc = 1? ackd = 1? chapter 15 i 2 c bus user?s manual u15905ej2v1ud 401 15.16 timing of data communication when using i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the mast er device transmits the trc bit (bit 3 of the iic status register (iics)), which specifies the data transfer di rection and then starts serial communication with the slave device. the shift operation of the iic bus shift register (iic) is syn chronized with the falling edge of the serial clock (scl). the transmit data is transferred to the so la tch and is output (msb first) via the sda pin. data input via the sda pin is captured by iic at the rising edge of scl. the data communication timing is shown below. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 402 figure 15-19. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (1/3) (a) start condition ~ address iic ackd std spd wtim h h l l l l h h h l l acke msts stt spt wrel intiic trc iic ackd std spd wtim acke msts stt spt wrel intiic trc scl sda processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic address iic data iic ffh transmit start condition receive (when exc = 1) note note note to cancel slave wait, write ffh to iic or set wrel. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 403 figure 15-19. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (2/3) (b) data iic ackd std spd wtim h h l l l l l l h h h h l l l l l acke msts stt spt wrel intiic trc iic ackd std spd wtim acke msts stt spt wrel intiic trc scl sda processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic data iic ffh note iic ffh note iic data transmit receive note note note to cancel slave wait, write ffh to iic or set wrel. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 404 figure 15-19. example of master to slave communication (when 9-clock wait is selected fo r both master and slave) (3/3) (c) stop condition iic ackd std spd wtim h h l l l l h h h l acke msts stt spt wrel intiic trc iic ackd std spd wtim acke msts stt spt wrel intiic trc scl sda processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic data iic address iic ffh note iic ffh note stop condition start condition transmit note note (when spie = 1) receive (when spie = 1) note to cancel slave wait, write ffh to iic or set wrel. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 405 figure 15-20. example of slave to master communication (when 9-clock wait is selected fo r both master and slave) (1/3) (a) start condition ~ address iic ackd std spd wtim h h l l h h l acke msts stt l l spt wrel intiic trc iic ackd std spd wtim acke msts stt spt wrel intiic trc scl sda processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iic address iic ffh note note iic data start condition note to cancel master wait, write ffh to iic or set wrel. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 406 figure 15-20. example of slave to master communication (when 9-clock wait is selected fo r both master and slave) (2/3) (b) data iic ackd std spd wtim h h h l l l l l l h h h l l l l l acke msts stt spt wrel intiic trc iic ackd std spd wtim acke msts stt spt wrel intiic trc scl sda processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic data iic data iic ffh note iic ffh note note to cancel master wait, write ffh to iic or set wrel. chapter 15 i 2 c bus user?s manual u15905ej2v1ud 407 figure 15-20. example of slave to master communication (when 9-clock wait is selected fo r both master and slave) (3/3) (c) stop condition iic ackd std spd wtim h h l l l h acke msts stt spt wrel intiic trc iic ackd std spd wtim acke msts stt spt wrel intiic trc scl sda processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic address iic ffh note note iic data stop condition start condition (when spie = 1) n- ack (when spie = 1) note to cancel master wait, write ffh to iic or set wrel. user?s manual u15905ej2v1ud 408 chapter 16 dma functions (dma controller) the v850es/sa2 and v850es/sa3 include a direct memory access (dma) controller (dmac) that executes and controls dma transfer. the dmac controls data transfer between memory and i/o, between memo ries, or between i/os based on dma requests issued by the on-chip peripher al i/o (serial interface, real-time pulse unit, and a/d converte r), interrupts from external input pins, or software triggers (memory refers to internal ram or external memory). 16.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65,536 (2 16 ) ? transfer type: two-cycle transfer ? transfer mode: single transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/o (seria l interface, timer/counter, a/d converter) or interrupts from external input pin ? requests by software trigger ? transfer objects ? internal ram ? internal peripheral i/o ? peripheral i/o ? internal peripheral i/o ? internal ram ? external memory ? external memory ? internal peripheral i/o ? external memory ? external memory chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 409 16.2 configuration cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850es/sa2, v850es/sa3 bus interface external bus external ram external rom external i/o dma source address register n (dsanh/dsanl) dma transfer count register n (dbcn) dma channel control register n (dchcn) dma destination address register n (ddanh/ddanl) dma addressing control register n (dadcn) dma trigger factor register n (dtfrn) remark n = 0 to 3 chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 410 16.3 control registers 16.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) these registers are used to set the dma source addresses (28 bits each) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, dsanh and dsanl. (1) dma source address registers 0h to 3h (dsa0h to dsa3h) these registers can be read or written in 16-bit units. dsanh (n = 0 to 3) external memory, on-chip peripheral i/o internal ram ir 0 1 dma source address specification sets the dma source addresses (a25 to a16). during dma transfer, it stores the next dma transfer source address. sa25 to sa16 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir 0 0 0 0 0 sa25 sa24 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 (2) dma source address registers 0l to 3l (dsa0l to dsa3l) these registers can be read or written in 16-bit units. dsanl (n = 0 to 3) after reset: undefined r/w address: dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 sa14 sa13 sa12 sa11 sa10 sa9 sa8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 sets the dma source addresses (a15 to a0). during dma transfer, it stores the next dma transfer source address. sa15 to sa0 chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 411 16.3.2 dma destination address regi sters 0 to 3 (dda0 to dda3) these registers are used to set the dma destination address (28 bits each) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, ddanh and ddanl. (1) dma destination address register s 0h to 3h (dda0h to dda3h) these registers can be read or written in 16-bit units. ddanh (n = 0 to 3) external memory, on-chip peripheral i/o internal ram ir 0 1 dma destination address specification after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, dda2h fffff096h, dda3h fffff09eh da23 da22 da21 da20 da19 da18 da17 da16 ir 0 0 0 0 0 da25 da24 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 sets the dma destination addresses (a25 to a16). during dma transfer, it stores the next dma transfer destination address. da25 to da16 (2) dma destination address regist ers 0l to 3l (dda0l to dda3l) these registers can be read or written in 16-bit units. ddanl (n = 0 to 3) after reset: undefined r/w address: dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch da7 da6 da5 da4 da3 da2 da1 da0 da15 da14 da13 da12 da11 da10 da9 da8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 sets the dma destination addresses (a15 to a0). during dma transfer, it stores the next dma transfer destination address. da15 to da0 chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 412 16.3.3 dma byte count registers 0 to 3 (dbc0 to dbc3) these 16-bit registers are used to set the byte transfer co unt for dma channels n (n = 0 to 3). they store the remaining transfer count during dma transfer. these registers can be read or written in 16-bit units. remark if the dbcn register is read during dma transfer a fter a terminal count has occurred without the register being overwritten, the value set immediately before the dma transfer will be read out (0000h will not be read, even if dma transfer has ended). dbcn (n = 0 to 3) byte transfer count 1 or remaining byte transfer count byte transfer count 2 or remaining byte transfer count : byte transfer count 65,536 (2 16 ) or remaining byte transfer count bc15 to bc0 0000h 0001h : ffffh byte transfer count setting or remaining byte transfer count during dma transfer after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 413 16.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) these 16-bit registers are used to co ntrol the dma transfer mode for dma channel n (n = 0 to 3). these registers cannot be accessed during dma operation. they can be read or written in 16-bit units. dadcn (n = 0 to 3) 8 bits 16 bits ds0 0 1 setting of transfer data size for dma transfer increment decrement fixed setting prohibited sad1 0 0 1 1 sad0 0 1 0 1 setting of count direction of the source address for dma channel n increment decrement fixed setting prohibited dad1 0 0 1 1 dad0 0 1 0 1 setting of count direction of the destination address for dma channel n after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h sad1 sad0 dad1 dad0 0 0 0 0 0ds000 00 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 414 16.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) these 8-bit registers are used to c ontrol the dma transfer operating mode for dma channel n (n = 0 to 3). these registers can be read or written in 8-bit or 1-bit units. (however, bit 7 is read-only and bits 1 and 2 are write- only. if bit 1 or 2 is read, the read value is always 0.) dchcn (n = 0 to 3) dma transfer had not ended. dma transfer had ended. it is set to 1 when dma transfer ends and cleared (to 0) when it is read. tcn 0 1 status flag indicates whether dma transfer through dma channel n has ended or not initn when changing the ddanh, ddanl, dsanl, dsanh, or dbcn register before the number of transfers set by dbcn has finished, set this bit to 1 to initialize dma. dma transfer disabled dma transfer enabled this bit is cleared to 0 when dma transfer ends. enn 0 1 setting of whether dma transfer through dma channel n is to be enabled or disabled after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h tcn note 1 0 0 0 0 initn note 2 stgn note 2 enn <0> <1> <2> 3 4 5 6 <7> set the init bit to 1 when the enn bit is 0. if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. stgn notes 1. the tcn bit is read-only. 2. the initn and stgn bits are write-only. caution before generating a dma tran sfer request by software, make sure that the tcn bit is set to 1 and then clear the tcn bit to 0. remark if the completion of dma transfer and the bit mani pulation instruction for the dchcn register conflict, the enn bit may not be cleared. chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 415 16.3.6 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) these 8-bit registers are used to control the dma transfe r start trigger through interrupt requests from on-chip peripheral i/o. the interrupt requests set with these regist ers serve as dma transfer start factors. these registers can be read or written in 8-bit or 1-bit unit s. however, only bit 7 (dfn) can be read/written in 1-bit units. dtfrn (n = 0 to 3) no dma transfer request dma transfer request dfn note 0 1 setting of interrupt source that serves as the dma start factor after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 0 1 2 3 4 5 6 <7> note the dfn bit is a write-only bit. write 0 to this bit to clear a dma transfer request if the interrupt that is specified as the cause of starting dma transfer while dma transfer is disabled. cautions 1. be sure to stop dma operation befo re making changes to dtfrn register settings. 2. an interrupt request input in a standby mode (idle or software stop mode) cannot be used as a dma transfer start factor. 3. for details of ifcn5 to ifcn0 bits , refer to table 16-1 dma start factor. remark n = 0 to 3 chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 416 table 16-1. dma start factor ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request by interrupt disabled 0 0 0 0 0 1 intwdtm 0 0 0 0 1 0 intp0 0 0 0 0 1 1 intp1 0 0 0 1 0 0 intp2 0 0 0 1 0 1 intp3 0 0 0 1 1 0 intp4 0 0 0 1 1 1 intp5 0 0 1 0 0 0 intp6 0 0 1 0 0 1 intrtc 0 0 1 0 1 0 intcc00 0 0 1 0 1 1 intcc01 0 0 1 1 0 0 intovf0 0 0 1 1 0 1 intcc10 0 0 1 1 1 0 intcc11 0 0 1 1 1 1 intovf1 0 1 0 0 0 0 inttm2 0 1 0 0 0 1 inttm3 0 1 0 0 1 0 inttm4 0 1 0 0 1 1 inttm5 0 1 0 1 0 0 intcsi0 0 1 0 1 0 1 intiic 0 1 0 1 1 0 intcsi1 0 1 0 1 1 1 intsre0 0 1 1 0 0 0 intsr0 0 1 1 0 0 1 intst0 0 1 1 0 1 0 intcsi2 0 1 1 0 1 1 intsre1 0 1 1 1 0 0 intsr1 0 1 1 1 0 1 intst1 0 1 1 1 1 0 intcsi3 0 1 1 1 1 1 intcsi4 1 0 0 0 0 0 intad 1 0 0 0 0 1 intovf 1 0 0 0 1 0 intbrg 1 0 0 1 1 1 setting prohibited after this remark n = 0 to 3 chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 417 16.4 dma bus states 16.4.1 types of bus states the dmac bus states consis t of the following 10 states. (1) ti state the ti state is an idle state, duri ng which no access request is issued. the dma request signals are sampled at the rising edge of the clkout signal. (2) t0 state dma transfer ready state (state in which a dma transfe r request has been issued and the bus mastership is acquired for the first dma transfer). (3) t1r state the bus enters the t1r state at the beginning of a read operation in the two-cycle transfer mode. address driving starts. after entering the t1r st ate, the bus invariably enters the t2r state. (4) t1ri state the t1ri state is a state in which the bus waits for the acknowledge signal corresponding to an external memory read request. after entering the last t1ri state, t he bus invariably enters the t2r state. (5) t2r state the t2r state corresponds to the last state of a read operation in the tw o-cycle transfer mode, or to a wait state. in the last t2r state, read data is sampled. after ent ering the last t2r state, the bus invariably enters the t1w state. (6) t2ri state state in which the bus is re ady for dma transfer to on-c hip peripheral i/o or internal ram (state in which the bus mastership is acquired for dma transfer to on-chip peripheral i/o or internal ram). after entering the last t2ri state, t he bus invariably enters the t1w state. (7) t1w state the bus enters the t1w state at the beginning of a write operatio n in the two-cycle transfer mode. address driving starts. after entering the t1w st ate, the bus invariably enters the t2w state. (8) t1wi state state in which the bus waits for the acknowledge signal corresponding to an external memory write request. after entering the last t1wi state, t he bus invariably enters the t2w state. (9) t2w state the t2w state corresponds to the last state of a write operation in the tw o-cycle transfer mode, or to a wait state. in the last t2w state, the writ e strobe signal is made inactive. (10) te state the te state corresponds to dma transfer completion . the dmac generates the internal dma transfer completion signal and various internal signals are initializ ed (n = 0 to 3). after entering the te state, the bus invariably enters the ti state. chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 418 16.4.2 dmac bus cycle state transition except for the block transfer mode, each time the processi ng for a dma transfer is completed, the bus mastership is released. figure 16-1. dmac bus cycle (two-c ycle transfer) state transition ti t0 t1r t1ri t2r t1w t2w te ti t2ri t1wi chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 419 16.5 transfer mode 16.5.1 single transfer mode in single transfer mode, the dmac releases the bus at eac h byte/halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. th is operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. 16.6 transfer types 16.6.1 two-cycle transfer in two-cycle transfer, data transfer is performed in two cy cles, a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and readin g is performed from the source to the dmac. in the second cycle, the destination address is output and writi ng is performed from the dmac to the destination. chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 420 16.7 transfer object 16.7.1 transfer type and transfer object table 13-2 shows the relationship between transfer type and transfer object ( : transfer enabled, : transfer disabled). table 16-2. relationship between tr ansfer type and transfer object destination internal rom on-chip peripheral i/o external i/o internal ram external memory on-chip peripheral i/o external i/o internal ram external memory source internal rom caution the operation is not guaranteed for combinat ions of transfer destination and source marked with ? ? in table 16-2. remark during two-cycle 16-bit transfer, if the data bus width of the transfer source and that of the transfer destination are different, the operation becomes as follows. in the case of transfer from a 16-bit bus to an 8-bit bus a 16-bit read cycle is generated and then an 8-bit write cycle is generated twice. in the case of transfer from an 8-bit bus to a 16-bit bus an 8-bit read cycle is generated twice an d then a 16-bit write cycle is generated. 16.7.2 external bus cycles during dm a transfer (two-cycle transfer) the external bus cycles during dma transfe r (two-cycle transfe r) are shown below. table 16-3. external bus cycles duri ng dma transfer (two-cycle transfer) transfer object external bus cycle on-chip peripheral i/o, internal ram none note ? external i/o yes sram cycle external memory yes memory access cycle set by the bct register note other external cycles such as a cpu-based bus cycle can be started. chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 421 16.8 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 these priorities are valid in the ti state only. in the block transfer mode , the channel used for transfer is never switched. 16.9 dma transfer start factors there are two types of dma transfe r start factors, as shown below. (1) request from software if the stgn, enn, and tcn bits of t he dchcn register are set as follows, dma transfer starts (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 (2) request from on-chip peripheral i/o if, when the enn and tcn bits of the dchcn register are set as shown bel ow, an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0 16.10 dma transfer end 16.10.1 dma transfer end interrupt when dma transfer ends and the tcn bit of the dchcn register is set to 1, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc) (n = 0 to 3). 16.10.2 terminal count output upon dma transfer end the terminal count signal becomes active fo r one clock during the last dma transfer cycle. chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 422 16.11 precautions (1) the transfer operation is not guar anteed if the source or the destination address exceeds the area of dma objects (external memory, internal ram, or peripheral i/o) during dma transfer. (2) dma transfer of 16-bit bus width misaligned data is not supported. (3) the time required to respond to a dma request, and the minimum number of clocks required for dma transfer are shown below. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note 1 + transfer destination memory access (<2>) dma cycle minimum number of execution clocks <1> dma request response time 4 clocks (min.) + noise elimination time note 2 external memory access depends on connected memory. internal ram access 2 clocks note 3 <2> memory access peripheral i/o register access 3 clocks + number of wait cycles specified by vswc register note 4 notes 1. one clock is always inserted between a read cycle and a write cycle in dma transfer. 2. if an external interrupt (intpn) is specified as the tr igger to start dma transfer, noise elimination time is added (n = 0 to 7). 3. two clocks are required for a dma cycle. 4. more wait cycles are necessary for accessing a specia l internal peripheral i/o register (for details, refer to 3.4.8 (2) ). (4) the cpu can access external memory, on-chip peri pheral i/o, and internal ram not undergoing dma transfer. while data transfer among external memories or to and from i/o is being performed, t he cpu can access internal ram. while data transfer is being exec uted between internal rams, the cpu can access external memory and peripheral i/o. (5) set the vswc register to 00h or 01h. fo r details of the vswc register, refer to chapter 5 bus control function . (6) set the dsan, ddan, dbcn, and dadcn registers at any of the following timing other than during dma operation. ? after reset and before the first dma transfer starts ? after the channel has been initialized and before the first dma transfer starts ? after dma transfer is complete (the tcn bit of the dc hcn register is 1) and before the next dma transfer start request is generated (7) if the dsan or ddan register is read during dm a transfer, the value being updated may be read. chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 423 (8) dma transfer in progress can be stopped by clearing the enn bit of the dchcn register to 0 during dma transfer. follow either of the procedures below to cl ear the enn bit of the dchcn register to 0. (a) to discard all transfers in progress a nd start dma transfer from the beginning <1> stop generation of the dma transfer start factor (stop the dma operation). <2> make sure that the dfn bit of the dtfrn regi ster is cleared to 0 (clear the bit if set). <3> after making sure that the dfn bit of the dtfrn register is cleared to 0, clear the enn bit of the dchcn register to 0. <4> set the initn bit of the dchcn register (thi s operation initializes the transfer status). (b) to interrupt and resume the transfer in progress <1> stop generation of the dma transfer start factor (stop the dma operation). <2> make sure that the dfn bit of the dtfrn register is cleared to 0 (if set, wait until the pending dma transfer requests have been completed). <3> after making sure that the dfn bit of the dtfrn register is cleared to 0, clear the enn bit of the dchcn register to 0 (this operation interrupts dma transfer). <4> set the enn bit of the dchcn regist er to 1 to resume dma transfer. <5> start the operation of the dma tr ansfer start factor that was stopped. (9) the init bit is used to initialize dma; however, if the setting of the init bit and the dma transfer of another channel conflict, initialization processi ng is not performed. set the init bi t following either of the procedures below. (a) to temporarily stop the tr ansfers of all dma channels <1> disable interrupts (di). <2> read the enn bits of the dchcn registers of t he dma channels in use other than the channel to be initialized and transfer the read value to a general-purpose register. <3> clear the enn bits of the dma channels in use (inclu ding the channel to be initialized) to 0. for the last dma channel, execute the clear instruction for the enn bit twice note . for example, execute the following instruct ions when channels 0, 1, and 2 are used. ? clear e00 of the dchc0 register to 0 ? clear e11 of the dchc1 register to 0 ? clear e22 of the dchc2 register to 0 ? clear e22 of the dchc2 register to 0 <4> set the initn bit of the channel to be initialized to 1. <5> read the tcn bit of each of the channels not to be forcibly stopped. if the tcn and enn bits of each channel not to be initialized, and the read tcn bi t and the value read in <2> are 1 (the anded values are 1), clear the saved enn bit to 0. <6> write the values of the enn bits manipula ted in step <5> above to the dchcn register. <7> enable interrupts (ei). note if the transfer target (transfer source or transfe r destination) is the internal ram, execute the instruction three times. caution 1. always perform step <5> to preven t the enn bit of the channels successfully completed in <2> and <3> from being illegally set. chapter 16 dma functions (dma controller) user?s manual u15905ej2v1ud 424 caution 2. do not configure programs that exp ect the tcn bit of the dchcn register to be set to 1 by other than the above proces sing (the tcn bit of the dchcn register is cleared to 0 after a read, so the bit is cleared when the inst ruction in <5> has been executed). (b) to repetitively set the initn bit until dma is successfully initialized <1> clear the enn bit of the dchcn register of the channel to be initialized to 0. <2> clear the enn bit of the dchcn register of the channel to be initialized to 0. if the transfer target of the channel to be initiali zed (transfer source or transfer destination) is the internal ram, clear the enn bit of the dchcn register to 0 once again. <3> copy the number of initial transfers of the cha nnel to be initialized to a general-purpose register. <4> set the initn bit of the channel to be initialized to 1. <5> read the value of the dma transfer count regist er (dbcn) of the channel to be initialized and compare it with the value copied in step <3>. if these values do not matc h, repeat steps <4> and <5>. (10) when dma transfer is complete, update is performed in the order of clearing the enn bit of the dchcn register to 0 and then setting the tcn bit to 1. therefore, the status of enn bit = tcn bit = 0 may be read depending on the timing of reading the dchcn register. (11) when the tcn bit of the dchcn register is confirmed to be set to 1 after reading the bit, read the tcn bit three more times. (12) the shortest interval for requesting dma transfer to the same channel varies depending on the bus wait setting during the read cycle/write cycle, activation status of other channels, and ex ternal bus hold request. input a sufficiently long interval for a transfer request to the same channel so that the bus cycle can be completed in the system. (13) do not apply start factors (hardware trigger, softwar e trigger) to the same channel at the same time. if two start factors are generated for one channel, only one or th e other factor is valid. t herefore, the entire system may not operate normally. (14) before starting dma transfer by manipulating the stgn bit (setting the stgn bit of the dchcn register to 1), perform a second or subsequent transfer after maki ng sure that the previous dma transfer has been completed (check the dbcn register or the tcn bit of the dchcn register). (15) when performing dma transfer whose target is the intern al ram while an instruction from the internal ram is in progress, do not include bit manipulation instructions and misalign access in the program that executes instructions from the internal ram. 16.11.1 interrupt factors dma transfer is interrupted if a bus hold is issued. if the factor (bus hold) interrupting dma transfe r disappears, dma transfer promptly restarts. user?s manual u15905ej2v1ud 425 chapter 17 interrupt/except ion processing function the v850es/sa2 and v850es/sa3 are provided with a dedicated interrupt controller (intc) for interrupt servicing and can process a total of 38 to 40 interrupt requests. an interrupt is an event that occurs independently of program execution, and an ex ception is an event whose occurrence is dependent on program execution. the v850es/sa2 and v850es/sa3 can pr ocess interrupt requests from t he on-chip peripheral hardware and external sources. moreover, exception processing can be st arted by the trap instruction (software exception) or by generation of an exception event (i.e. fetc hing of an illegal opcode) (exception trap). 17.1 features interrupts external interrupts: 8 sources (including nmi) internal interrupts: pd703200, 703201, 70f3201: 30 sources pd703200y, 703201y, 70f3201y: 31 sources pd703204, 70f3204: 31 sources pd703204y, 70f3204y: 32 sources 8 levels of programmable priorities (maskable interrupts) multiple interrupt control according to priority masks can be specified for eac h maskable interrupt request. noise elimination, edge detection, and valid edge specification for external interrupt request signals. exceptions software exceptions: 32 sources exception trap: 2 sources (illegal opcode exception, debug trap) interrupt/exception sources are listed in table 17-1. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 426 table 17-1. interrupt source list (1/2) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register reset pin input pin ? reset interrupt ? reset wdt overflow note 1 (wdtres) wdt 0000h 00000000h undefined ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt wdt overflow wdt 0020h 00000020h nextpc ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal opcode/ dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm interval timer overfl ow wdt 0080h 00000080h nextpc wdtic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin valid edge inpu t pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin valid edge inpu t pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin valid edge input pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin valid edge inpu t pin 00f0h 000000f0h nextpc pic6 8 intrtc rtc interrupt rtc 0100h 00000100h nextpc rtcic 9 intcc00 cc00 capture trigger input/ tm0-cc00 match tm0 0110h 00000110h nextpc ccic00 10 intcc01 cc01 capture trigger input/ tm0-cc01 match tm0 0120h 00000120h nextpc ccic01 11 intovf0 tm0 overflow tm 0 0130h 00000130h nextpc ovfic0 12 intcc10 cc10 capture trigger input/ tm1-cc10 match tm1 0140h 00000140h nextpc ccic10 13 intcc11 cc11 capture trigger input/ tm1-cc11 match tm1 0150h 00000150h nextpc ccic11 14 intovf1 tm1 overflow tm 1 0160h 00000160h nextpc ovfic1 15 inttm2 tm2-cr2 match/ tm2 overflow tm2 0170h 00000170h nextpc tmic2 16 inttm3 tm3-cr3 match/ tm3 overflow tm3 0180h 00000180h nextpc tmic3 17 inttm4 tm4-cr4 match/ tm4 overflow tm4 0190h 00000190h nextpc tmic4 18 inttm5 tm5-cr5 match/ tm5 overflow tm5 01a0h 000001ah nextpc tmic5 19 intcsi0 csi0 transfer completion csi0 01b0h 000001b0h nextpc csiic0 20 intiic note 3 i 2 c transfer completion i 2 c 01c0h 000001c0h nextpc iicic0 21 intcsi1 csi1 transfer completion csi1 01d0h 000001d0h nextpc csiic1 22 intsre0 uart0 reception error ua rt0 01e0h 000001e0h nextpc sreic0 23 intsr0 uart0 reception completi on uart0 01f0h 000001f0h nextpc sric0 24 intst0 uart0 transmission completion uart0 0200h 00000200h nextpc stic0 maskable interrupt 25 intcsi2 csi2 transfer completi on csi2 0210h 00000210h nextpc csiic2 notes 1. execute a system reset after interrup t servicing is finished. it is impossible to restore by executing the reti instruction. 2. n = 0 to fh 3. pd703200y, 703201y, 70f3201y, 703204y, 70f3204y only chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 427 table 17-1. interrupt source list (2/2) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 26 intsre1 uart1 reception error uart1 0220h 00000220h nextpc sreic1 27 intsr1 uart1 reception completi on uart1 0230h 00000230h nextpc sric1 28 intst1 uart1 transmission completion uart1 0240h 00000240h nextpc stic1 29 intcsi3 csi3 transfer completion csi3 0250h 00000250h nextpc csiic3 30 intcsi4 note csi4 transfer completion csi4 0260h 00000260h nextpc csiic4 31 intad a/d conversion completi on adc 0270h 00000270h nextpc adic 32 intdma0 dma0 transfer completi on dma 0280h 00000280h nextpc dmaic0 33 intdma1 dma1 transfer completi on dma 0290h 00000290h nextpc dmaic1 34 intdma2 dma2 transfer completion dma 02a0h 000002a0h nextpc dmaic2 35 intdma3 dma3 transfer completion dma 02b0h 000002b0h nextpc dmaic3 36 introv rtc overflow rtc 02c0h 000002c0h nextpc rovic maskable interrupt 37 intbrg brg match brg 02d 0h 000002d0h nextpc brgic note v850es/sa3 only remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of t he program counter (pc) saved to eipc or fepc when interrupt processing is started. note, however, that the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextpc (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the proc essing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 428 17.2 non-maskable interrupts a non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence ov er all the other interrupts. this product has the following two non-maskable interrupts. ? nmi pin input (nmi) ? non-maskable interrupt request generated by overflow of watchdog timer (intwdt) the valid edge of the nmi pin can be selected from four types: ?rising edge? , ?falling edge?, ?both edges?, and ?no edge detection?. the non-maskable interrupt generated by overflow of the watchdog timer (intwdt) functions when the wdtm4 and wdtm3 bits of the watchdog timer mode register (wdtm) are set to ?10?. if two or more non-maskable interrupts occur at the same time , the interrupt with the higher priority is serviced, as follows (the interrupt with the lower priority is ignored). intwdt > nmi if a new nmi or intwdt request is issued while a nmi is being serviced, it is serviced as follows. (1) if new nmi request is issued while nmi is being serviced the new nmi request is held pending, regardless of the va lue of the np bit of the program status word (psw) in the cpu. the pending nmi interrupt is acknowle dged after the nmi currently under execution has been serviced (after the reti instruction has been executed). (2) if intwdt request is issu ed while nmi is being serviced the intwdt request is held pending if the np bit of t he psw remains set (1) while the nmi is being serviced. the pending intwdt request is acknowledged after the nmi currently under ex ecution has been serviced (after the reti instruction has been executed). if the np bit of psw is cleared (0) while the nmi is being serviced, the newly generated intwdt request is executed (the nmi servicing is stopped). caution if a non-maskable interrupt request is genera ted, the values of the pc and psw are saved to the nmi status save registers (fepc and fepsw). at this time, execution can be returned by the reti instruction only from an nmi. executi on cannot be returned while intwdt is being serviced. therefore, reset the system after the interrupt has been serviced. figure 17-1. non-maskable interrupt re quest acknowledgment operation (1/2) (a) nmi and intwdt requests generated at the same time main routine system reset nmi and intwd t requests (generated simultaneously) intwd t servicing chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 429 figure 17-1. non-maskable interrupt re quest acknowledgment operation (2/2) (b) non-maskable interrupt request gene rated during non-maskable interrupt servicing non-maskable interrupt being serviced non-maskable interrupt request generated during non-maskable interrupt servicing nmi intwdt nmi ? nmi request generated during nmi servicing ? intwdt request generated during nmi servicing (np = 1 retained before intwdt request) main routine nmi request nmi servicing (held pending) servicing of pending nmi nmi request main routine system reset nmi request nmi servicing (held pending) intwdt servicing intwdt request ? intwdt request generated during nmi servicing (np = 0 set before intwdt request) main routine system reset nmi request nmi servicing intwdt servicing intwdt request np = 0 ? intwdt request generated during nmi servicing (np = 0 set after intwdt request) main routine system reset nmi request nmi servicing intwdt servicing np = 0 ? intwdt request generated during intwdt servicing main routine system reset intwdt request intwdt servicing (invalid) intwdt request ? nmi request generated during intwdt servicing intwdt main routine system reset intwdt request intwdt servicing (invalid) nmi request (held pending) intwdt request chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 430 17.2.1 operation if a non-maskable interrupt is generated by nmi input, th e cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code 0010h to the higher halfword (fecc) of ecr. <4> sets the np and id bits of the psw and clears the ep bit. <5> sets the handler address (00000010h, 00000020h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non- maskable interrupt is shown below. figure 17-2. servicing configurat ion of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h 1 0 1 00000010h, 00000020h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 431 17.2.2 restore (1) from nmi execution is restored from the nmi by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from fepc and fepsw, respectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. <2> transfers control back to the address of the restored pc and psw. the following illustrates how the re ti instruction is processed. figure 17-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit an d psw.np bit are changed by the ldsr instruction during non- maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is n ecessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. (2) from intwdt execution cannot be returned from intwdt by the reti in struction. execute a system reset after the interrupt has been serviced. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 432 17.2.3 np flag the np flag is a status flag that indicates that non -maskable interrupt servicing is under execution. this flag is set when a non-maskable interrupt request has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. 0 np ep id sat cy ov s z psw no nmi interrupt servicing nmi interrupt currently being serviced np 0 1 nmi interrupt servicing status after reset: 00000020h chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 433 17.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. the v850es/sa2 and v850es/sa3 have 38 to 40 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). when an interrupt request has been acknowledged, the acknow ledgment of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt service routine, the interr upt enabled (ei) status is set, which enables servicing of interrupts having a higher priority than the interrupt request in progress (specified by the interrupt control register). note that only in terrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to enable multiple interrupts, however, save eipc and eipsw to memory or registers before executing the ei instruction, and execute the di instruction before the reti instruction to restore the original values of eipc and eipsw. if the wdtm4 bit of the watchdog timer mode register (wdtm) is cleared to 0, the watchdog timer overflow interrupt functions as a maskable interrupt (intwdtm). 17.3.1 operation if a maskable interrupt occurs by int input, the cpu perfor ms the following processing, and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the id bit of the psw and clears the ep bit. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the maskable interrupt request masked by intc and th e maskable interrupt request generated while another interrupt is being serviced (while psw.np = 1 or psw.id = 1) are held pending inside intc. in this case, servicing a new maskable interrupt is started in acco rdance with the priority of the pending ma skable interrupt request if either the maskable interrupt is unmasked or psw.np and psw.id are cl eared to 0 by using the reti or ldsr instruction. how maskable interrupts are serviced is illustrated below. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 434 figure 17-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc accepted yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address note for the ispr register, see 17.3.6 in-service priority register (ispr) . the int input masked by the interrupt controllers and the int input that occurs while another interrupt is being serviced (when psw.np = 1 or psw.id = 1) are held pending intern ally by the interrupt controll er. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new maskable interrupt servicing. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 435 17.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is executed , the cpu performs the following steps, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 0 and the np bit of the psw is 0. <2> transfers control to the address of the restored pc and psw. the following illustrates the proce ssing of the reti instruction. figure 17-5. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, see 17.3.6 in-service priority register (ispr) . caution when the psw.ep bit an d the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is n ecessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 436 17.3.3 priorities of maskable interrupts the v850es/sa2 and v850es/sa3 provide multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple in terrupts can be controlled by priority levels. there are two types of priority level c ontrol: control based on the default pr iority levels, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn) of the interrupt control register (xxicn). when two or more interrupts hav ing the same priority level specified by the xxprn bit are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) befor ehand. for more in formation, refer to table 17-1 interrupt source list . the programmable priority control customizes interrupt r equests into eight levels by setting the priority level specification flag. note that when an interrupt request is acknowledged, the id flag of psw is automatically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 bef orehand (for example, by plac ing the ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (ad, brg, cc, csi, dma, iic, ovf, p, rov, rtc, sre, st, tm, wdt) n: peripheral unit number (none or 0 to 3). chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 437 figure 17-6. example of processing in whic h another interrupt request is issued while an interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 438 figure 17-6. example of processing in whic h another interrupt request is issued while an interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 439 figure 17-7. example of servicing inte rrupt requests simultaneously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to c in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 440 17.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each in terrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. this register can be read or written in 8-bit or 1-bit units. this register is set to 47h after reset. caution read the xxifn bit of the xxicn register with interrupts disab led (di). if the xxifn bit is read with interrupts enabled (ei), a normal value may not be read when the timing of interrupt acknowledgment and reading of the bit conflict. xxifn interrupt request not issued interrupt request issued xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 interrupt servicing enabled interrupt servicing disabled (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest). specifies level 1. specifies level 2. specifies level 3. specifies level 4. specifies level 5. specifies level 6. specifies level 7 (lowest). xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff15ah <6> <7> note the flag xxlfn is reset automatically by the ha rdware if an interrupt request is acknowledged. remark xx: identification name of each pe ripheral unit (ov, p00 to p03, p10 to p13, cm, dma, csi, se, sr, st, ad) n: peripheral unit number (none or 0 to 3). the addresses and bits of the interrupt control registers are as follows. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 441 table 17-2. interrupt control register (xxicn) bit address register <7> <6> 5 4 3 2 1 0 fffff110h wdtic wdtif wdtmk 0 0 0 wdtpr2 wdtpr1 wdtpr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h rtcic rtcif rtcmk 0 0 0 rtcr2 rtcr1 rtcr0 fffff122h ccic00 ccif00 ccmk00 0 0 0 ccr002 ccr001 ccr000 fffff124h ccic01 ccif01 ccmk01 0 0 0 ccr012 ccr011 ccr010 fffff126h ovfic0 ovfif0 ovfm k0 0 0 0 ovfr02 ovfr01 ovfr00 fffff128h ccic10 ccif10 ccmk10 0 0 0 ccr102 ccr101 ccr100 fffff12ah ccic11 ccif11 ccmk11 0 0 0 ccr112 ccr111 ccr110 fffff12ch ovfic1 ovfif1 ovfm k1 0 0 0 ovfr12 ovfr11 ovfr10 fffff12eh tmic2 tmf2 tmmk2 0 0 0 tmpr22 tmpr21 tmpr20 fffff130h tmic3 tmf3 tmmk3 0 0 0 tmpr32 tmpr31 tmpr30 fffff132h tmic4 tmf4 tmmk4 0 0 0 tmpr42 tmpr41 tmpr40 fffff134h tmic5 tmf5 tmmk5 0 0 0 tmpr52 tmpr51 tmpr50 fffff136h csiic0 csiif0 csimk0 0 0 0 csipr02 csipr01 csipr00 fffff138h iicic note 1 iicif iicmk 0 0 0 iicpr2 iicpr1 iicpr0 fffff13ah csiic1 csiif1 csimk1 0 0 0 csipr12 csipr11 csipr10 fffff13ch sreic0 sreif0 sremk0 0 0 0 srepr02 srepr01 srepr00 fffff13eh sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff140h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff142h csiic2 csiif2 csimk2 0 0 0 csipr22 csipr21 csipr20 fffff144h sreic1 sreif1 sremk1 0 0 0 srepr12 srepr11 srepr10 fffff146h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff148h stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff14ah csiic3 csiif3 csimk3 0 0 0 csipr32 csipr31 csipr30 fffff14ch csiic4 note 2 csiif4 csimk4 0 0 0 csipr42 csipr41 csipr40 fffff14eh adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff150h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff152h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff154h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff156h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff158h rovic rovif rovmk 0 0 0 rovpr2 rovpr1 rovpr0 fffff15ah brgic brgif brgmk 0 0 0 brgpr2 brgpr1 brgpr0 notes 1. pd703200y, 703201y, 703204y, 70f3201y, 70f30204y only 2. v850es/sa3 only chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 442 17.3.5 interrupt mask register s 0 to 2 (imr0 to imr2) these registers set the interrupt mask state for the mask able interrupts. the xxmkn bit of the imr0 to imr2 registers is equivalent to the xxmkn bit of the xxicn register. the imrm register can be read or written in 16-bit units (m = 0 to 2). if the higher 8 bits of the imrm register are used as an imrmh register and the lower 8 bits as an imrml register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 2). bits 15 to 6 of the imr2 register (bits 7 to 0 of the imr2 h register and bits 7 and 6 of the imr2l register) are fixed to 1. if these bits are not 1, the operation cannot be guaranteed. these registers are set to ffffh after reset. caution the device file defines the xxmkn bit of the xxicn register as a reserved word. if a bit is manipulated using the name of xxmkn, the conten ts of the xxicn register, instead of the imrm register, are rewritten (as a resu lt, the contents of the imrm register are also rewritten). tmmk2 pmk6 imr0 ovfmk1 pmk5 ccmk11 pmk4 ccmk10 pmk3 ovfmk0 pmk2 ccmk01 pmk1 ccmk00 pmk0 rtcmk wdtmk after reset: ffffh r/w address: fffff100h after reset: ffffh r/w address: fffff102h after reset: ffffh r/w address: fffff104h admk srmk0 imr1 csimk4 note sremk0 csimk3 csimk1 stmk1 iicmk srmk1 csimk0 sremk1 tmmk5 csimk2 tmmk4 stmk0 tmmk3 1 1 xxmkn 0 1 interrupt servicing enabled interrupt servicing disabled imr2 1 1 1 brgmk 1 ovfmk 1 dmamk3 1 dmamk2 1 dmamk1 1 dmamk0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 interrupt mask flag setting 14 15 1 2 3 4 5 6 7 0 note this bit is valid only for the v850es/sa3. in the v850ea/sa2, be sure to set this bit to 1. remark xx: identification name of each pe ripheral unit (ad, brg, cc, csi, dma, iic, ovf, d, rov, rtc, sre, st, tm, wdt). n: peripheral unit number (none, or 0 to 3) chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 443 17.3.6 in-service priority register (ispr) this register holds the priority level of the maskable inte rrupt currently acknowledged. when an interrupt request is acknowledged, the bit of this register corresponding to the prio rity level of that interrupt request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically cleared to 0 by hardware. however, it is not cleared to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. this register is cleared to 00h after reset. caution when an interrupt is ackno wledged while the ispr register is being read with interrupts enabled (ei), the value of the ispr register after the bit has been set to 1 as a result of interrupt acknowledgment may be read. to correctly read th e values in the ispr register before interrupt acknowledgment, read the regist er with interrupts disabled (di). ispr7 interrupt request with priority n not acknowledged interrupt request with priority n acknowledged isprn 0 1 priority of interrupt currently acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah <7> <6> <5> <4> <3> <2> <1> <0> remark n = 0 to 7 (priority level) 17.3.7 id flag this flag controls the maskable interr upt?s operating state, and st ores control information regarding enabling or disabling of interrupt requests. an interrupt disable fl ag (id) is incorporated, which is assigned to the psw. 0 np ep id sat cy ov s z psw maskable interrupt request acknowledgment enabled maskable interrupt request acknowledgment disabled (pending) id 0 1 maskable interrupt servicing specification note after reset: 00000020h note interrupt disable flag (id) function this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instru ction when referencing the psw. non-maskable interrupt requests and exceptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during the acknowledgment disabled period (id = 1) is acknowledged when the xxifn bit of xxicn is set to 1, and the id flag is reset to 0. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 444 17.3.8 watchdog timer mode register (wdtm) this register is a special register and can be written only in a specific sequence. to generate a maskable interrupt (intwdt), clear the wdtm4 bit of this register to 0. this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset (for details, refer to chapter 10 watchdog timer functions ). run stops counting. clears counter and starts counting. run 0 1 watchdog timer operation mode selection note 1 wdtm 0 0 wdtm4 wdtm3 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (maskable interrupt intwdtm occurs if overflow occurs.) watchdog timer mode 1 (non-maskable interrupt intwdt occurs if overflow occurs.) watchdog timer mode 2 (reset operation wdtres is started if overflow occurs.) wdtm4 0 0 1 1 wdtm3 0 1 0 1 watchdog timer operation mode selection note 2 <7> chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 445 17.4 noise elimination at external interrupt request input pins the external interrupt request input pins (nmi, intp0 to intp6) incorporate noise elim inators that eliminate noise via analog delay. therefore, unless t he levels input to the nmi and intp0 to intp6 pins are retained for a certain length of time, the input cannot be detected as an ed ge. an edge is detected a certain time later. an external interrupt request input pin can also be used to cancel software stop mode. 17.4.1 edge detection function of exte rnal interrupt request input pins the valid edge of an external interrupt request input pin can be selected from "rising edge", "falling edge", "both edges", and "no edge detection". use rising edge specification register 0 (intr0) and falling edge specification re gister 0 (intf0) to specify the valid edges of non-maskable interrupts (nmi) and maskable interrupt s (intp0 to intp4). these registers can be read or written in 8-bit or 1-bit units. the nmi and intp0 to intp4 pins are set to "no edge detec tion" after reset; therefore, an interrupt request is not acknowledged unless the valid edge is enabled using the intf0 and intr0 registers (the ports function as normal ports). use rising edge specification register 9 (intr9) and falling edge specification re gister 9 (intf9) to specify the valid edges of maskable interrupts (intp5 and intp6). the intp5 and intp6 pins are set to "no edge detection" after reset; therefore, an interrupt request is not acknowledged unless the valid edge is enabled using the intf9 and intr9 registers (the ports function as normal ports). when using an external interrupt request input pin as an i/o port, set the valid edge of the nmi or intp0 to intp6 pins to "no edge detection". chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 446 (1) external interrupt rising edge specification register 0 (intr0) this is an 8-bit register that specifies detection of the rising edge of the nmi and intp0 to intp4 pins. this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear intf0n and intr0n to 0, and then set the port mode. 0 intr0 intp4 0 intr05 intr04 intr03 intr02 intr01 intr00 after reset: 00h r/w address: fffffc20h intp3 intp2 intp1 intp0 nmi remark for how to specify a valid edge, refer to table 17-3 . (2) external interrupt falling edge specification register 0 (intf0) this is an 8-bit register that specifies detection of the falling edge of the nmi and intp0 to intp4 pins. this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear intf0n and intr0n to 0, and then set the port mode. 0 intf0 0 intf05 intf04 intf03 intf02 intf01 intf00 after reset: 00h r/w address: fffffc00h intp4 intp3 intp2 intp1 intp0 nmi remark for how to specify a valid edge, refer to table 17-3 . table 17-3. valid edge specification intf0n intr0n valid edge specification (n = 0 to 5) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 0: control of nmi pin n = 1 to 5: control of intp0 to intp4 pins chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 447 (3) external interrupt rising edge specification register 9 (intr9) this is an 8-bit register that specifies detectio n of the rising edge of the intp5 and intp6 pins. this register can be read or written in 16-bit units. when the lower 8 bits of the intr9 register are used as intr9l register, however, it can be read or written in 8-bit or 1-bit units. this register is cleared to 0000h after reset. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear intf9n and intr9n to 0, and then set the port mode. intr9 (intr9l) after reset: 0000h r/w address: intr9: fffffc32h, intr9l: fffffc32h 0 0 0 0 intr93 intr92 0 0 00 00 00 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 intp6 intp5 remark for how to specify a valid edge, refer to table 17-4 . (4) external interrupt falling edge specification register 9 (intf9) this is an 8-bit register that specifies detectio n of the falling edge of the intp5 and intp6 pins. this register can be read or written in 16-bit units. when the lower 8 bits of the intf9 register are used as intf9l register, however, it can be read or written in 8-bit or 1-bit units. this register is cleared to 0000h after reset. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear intf9n and intr9n to 0, and then set the port mode. intf9 after reset: 0000h r/w address: intf9: fffffc12h, intf9l: fffffc12h 0 0 0 0 intf93 intf92 0 0 00 00 00 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 (intf9l) intp6 intp5 remark for how to specify a valid edge, refer to table 17-4 . table 17-4. valid edge specification intf9n intr9n valid edge specification (n = 2, 3) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 2, 3: control of intp5 and intp6 pins chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 448 17.5 software exception a software exception is generated when the cpu ex ecutes the trap instruction, and can always be acknowledged. 17.5.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfers control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the ep and id bits of the psw. <5> sets the handler address (00000040h or 00000050h ) corresponding to the software exception to the pc, and transfers control. the following illustrates the proce ssing of a software exception. figure 17-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 0 to 1fh.) the handler address is determined by the trap instruction? s operand (vector). if the vector is 0 to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 449 17.5.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instruction, t he cpu carries out the following processi ng and shifts control to the restored pc?s address. <1> loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. <2> transfers control to the address of the restored pc and psw. the following illustrates the proce ssing of the reti instruction. figure 17-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to r estore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 450 17.5.3 ep flag the ep flag is bit 6 of the psw, and is a status flag used to indicate that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress. exception processing in progress. ep 0 1 exception processing status after reset: 00000020h chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 451 17.6 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850es/sa2 and v850es/sa3, an illegal opcode exception (i lgop: illegal opcode trap) is considered as an exception trap. 17.6.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an instruction applicable to this illegal instruction is executed. 15 16 23 22 xxxxxx0 x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible to assign this instruction to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the followi ng processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> sets the handler address (00000060h) correspondi ng to the exception trap to the pc, and transfers control. the following illustrates the processing of the exception trap. chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 452 figure 17-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following proce ssing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. the following illustrates the restore processing from an exception trap. figure 17-11. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 453 17.6.2 debug trap a debug trap is an exception t hat occurs upon execution of the dbtr ap instruction and t hat can be acknowledged at all times. when a debug trap occurs, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> sets the handler address (00000060h) for the deb ug trap routine to the pc and transfers control. the following illustrates the debug trap processing flow. figure 17-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 454 (2) restore execution is restored from debug trap processing by the dbret instructi on. when the dbret instruction is executed, the cpu performs the following processing and tr ansfers control to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. the following illustrates the processing flow for restore from debug trap processing. figure 17-13. processing flow for restore from debug trap dbret instruction pc psw dbpc dbpsw jump to restored pc address chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 455 17.7 interrupt acknowledge time of cpu except the following cases, the interrupt acknowledge time of the cpu is 4 clocks minimum. to input interrupt requests successively, input the next interrupt at least 4 clocks after the preceding interrupt. ? in software/hardware stop mode ? when the external bus is accessed ? when interrupt request non-sampling instruct ions are successively executed (refer to 17.8 periods in which interrupts are not acknowledged by cpu .) ? when the interrupt control register is accessed ? when a peripheral i/o register is accessed figure 17-14. pipeline operation at inte rrupt request acknowledgment (outline) internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (start instruction of interrupt service routine) interrupt request if id ex df wb ifx idx 4 system clocks if if id ex int1 int2 int3 int4 remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt acknowledge time (internal system clock) internal interrupt external interrupt condition minimum 4 4 + analog delay time maximum 6 6 + analog delay time the following cases are exceptions. ? in idle/software stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession access to interrupt control register ? access to peripheral i/o register chapter 17 interrupt/exception processing function user?s manual u15905ej2v1ud 456 17.8 periods in which interrupts are not acknowledged by cpu an interrupt is acknowledged by the cpu while an instru ction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instructi on and the next instruction (int errupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the command register (prcmd) ? the load, store, or bit manipulation instructions for the following interrupt-related registers. interrupt control register (xxicn), interrupt mask register s 0 to 2 (imr0 to imr2), in-service priority register (ispr) user?s manual u15905ej2v1ud 457 chapter 18 standby function 18.1 overview the power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. the available stan dby modes are listed in table 18-1. table 18-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle mode mode to stop all the internal operations of the chip except the oscillator software stop mode mode to stop all the internal operations of the chip except the subclock oscillator subclock operation mode mode to use the subclock as the internal system clock sub-idle mode mode to stop all the internal operations of the chip, except the oscillator, in the subclock operation mode chapter 18 standby function user?s manual u15905ej2v1ud 458 figure 18-1. status transition normal operation mode (operation with main clock) wait for stabilization of oscillation wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count end of oscillation stabilization time count end of oscillation stabilization time count setting of halt mode interrupt request note 1 setting of stop mode idle mode halt mode software stop mode reset pin input reset interrupt request note 2 setting of idle mode interrupt request note 3 reset pin input notes 1. non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), or unmasked internal interrupt request from peripheral functions operable in idle mode. 2. non-maskable interrupt request, unmasked maskabl e interrupt request, or reset input by wdt overflow. 3. non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), or unmasked internal interrupt request from peripheral functions operable in software stop mode. chapter 18 standby function user?s manual u15905ej2v1ud 459 figure 18-2. status transition (during subclock operation) normal operation mode (operation with main clock) wait for stabilization of oscillation sub-idle mode subclock operation mode end of oscillation stabilization time count reset pin input setting of normal operation setting of subclock operation setting of idle mode interrupt request note reset pin input note non-maskable interrupt request (nmi pin input), unm asked external interrupt request (intp0 to intp6 pin input), or unmasked internal interrupt request from peripheral functions operable in sub-idle mode. chapter 18 standby function user?s manual u15905ej2v1ud 460 18.2 halt mode 18.2.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillator continues operating. only clock supply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 18-3 shows the operation status in the halt mode. the average power consumpti on of the system can be reduced by using the halt mode in combination with the normal operation mode for intermittent operation. caution insert five or more nop instru ctions after the halt instruction. 18.2.2 releasing halt mode the halt mode is released by a non-maskable interru pt request, an unmasked maskable interrupt request, reset pin input, and reset by the watchdog timer. after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-m askable interrupt request or unmasked maskable interrupt request the halt mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. if t he halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the halt mode is rel eased, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than th at of the interrupt request currently being serviced is issued (including a non-maskable interru pt request), the halt mode is re leased and that interrupt request is acknowledged. table 18-2. operation after releasi ng halt mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed chapter 18 standby function user?s manual u15905ej2v1ud 461 (2) releasing halt mode by reset pi n input and reset by watchdog timer the same operation as the normal reset operation is performed. table 18-3. operation status in halt mode setting of halt mode operation status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled cpu stops operation dma operable interrupt controller operable rom correction stops operation 16-bit timer/event counters (tm0, tm1) operable 8-bit timer/event counters (tm2 to tm5) operable real-timer counter operable when divided f x /brg output is selected as count clock operable watchdog timer operable csi0 to csi4 operable i 2 c note 1 operable serial interface uart0, uart1 operable a/d converter operable d/a converter normal mode: stops operation (output is retained) note 2 real-time output mode: operable external bus interface refer to chapter 5 bus control function . port function retains status before halt mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set. notes 1. pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only 2. if the halt mode is set immediately after the d/ a conversion has started (during conversion), the operation continues until the d/a conversion is comp leted, when the d/a conversion is completed, the output is retained. chapter 18 standby function user?s manual u15905ej2v1ud 462 18.3 idle mode 18.3.1 setting and operation status the idle mode is set by clearing the psm bit of the power save mode register (psmr) to 0 and setting the stp bit of the power save control register ( psc) to 1 in the normal operation mode. in the idle mode, the clock oscillator continues operation but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle mode was set are retained. the cpu and other on-chip peripheral functions st op operating. however, the on- chip peripheral functions that can operate with the subclock or an external clock continue operating. table 18-5 shows the operation status in the idle mode. the idle mode can reduce the power consumption more t han the halt mode because it stops the operation of the on-chip peripheral functions. the main clock osc illator does not stop, so t he normal operation mode can be restored without waiting for the oscillation stabilization ti me after the idle mode has been released, in the same manner as when the halt mode is released. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the idle mode. 18.3.2 releasing idle mode the idle mode is released by a non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), unm asked internal interrupt request from the peripheral functions operable in the idle mode, or reset input. after the idle mode has been released, th e normal operation mode is restored. (1) releasing idle mode by non-m askable interrupt request or unm asked maskable interrupt request the idle mode is released by a non-maskable interr upt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. if t he idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the idle mode is rel eased, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the idle mode is released and that interrupt request is acknowledged. table 18-4. operation after releasi ng idle mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed chapter 18 standby function user?s manual u15905ej2v1ud 463 (2) releasing idle mode by reset pin input the same operation as the normal reset operation is performed. table 18-5. operation status in idle mode setting of idle mode operation status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled cpu stops operation dma stops operation interrupt controller stops operation rom correction stops operation 16-bit timer/event counters (tm0, tm1) stops operation 8-bit timer/event counters (tm2 to tm5) stops operation real-time counter operable when divided f x /brg output is selected as count clock operable watchdog timer stops operation csi0 to csi4 operable when sckn input clock is selected as operation clock (n = 0 to 4) i 2 c note 1 stops operation serial interface uart0, uart1 stops operation a/d converter operable when f brg is selected as operation clock d/a converter stops operation (output is retained) note 2 external bus interface refer to chapter 5 bus control function . port function retains status before idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle mode was set. notes 1. pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only 2. if the idle mode is set immediately after the d/ a conversion has started (during conversion), the operation continues until the d/a conversion is comp leted, when the d/a conversion is completed, the output is retained. chapter 18 standby function user?s manual u15905ej2v1ud 464 18.4 software stop mode 18.4.1 setting and operation status the software stop mode is set when t he psm bit of the psmr register is set to 1 and the stp bit of the psc register is set to 1 in the normal operation mode. in the software stop mode, the subclock oscillator conti nues operating but the main clock oscillator stops. clock supply to the cpu and the on-chip pe ripheral functions is stopped. as a result, program execution is st opped, and the conten ts of the internal ram before the software stop mode was set are retained. the on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. table 18-7 shows the operation stat us in the software stop mode. because the software stop mode stops operation of the ma in clock oscillator, it reduces the power consumption to a level lower than the idle mode. if the subclock oscillator and external clock are not used, the power consumption can be minimized with only leakage current flowing. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the software stop mode. 18.4.2 releasing soft ware stop mode the software stop mode is released by a non-maskable in terrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), unmasked in ternal interrupt request from the peripheral functions operable in the software stop mode, or reset pin input. after the software stop mode has been released, the no rmal operation mode is restored after the oscillation stabilization time has been secured. (1) releasing software stop mode by non-maskable interrupt request or unmasked maskable interrupt request the software stop mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt reques t. if the software stop mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the software stop mode is released, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than th at of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the software stop mode is released and that interrupt request is acknowledged. table 18-6. operation after releasing so ftware stop mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed chapter 18 standby function user?s manual u15905ej2v1ud 465 (2) releasing software stop mode by reset pin input the same operation as the normal reset operation is performed. table 18-7. operation status in software stop mode setting of software stop mode operation status item when subclock is not used when subclock is used main clock oscillator stops operation subclock oscillator ? oscillation enabled cpu stops operation dma stops operation interrupt controller stops operation rom correction stops operation 16-bit timer/event counters (tm0, tm1) stops operation 8-bit timer/event counters (tm2 to tm5) stops operation real-time counter stops operation operable when f xt is selected as count clock watchdog timer stops operation csi0 to csi4 operable when sckn input clock is selected as operation clock (n = 0 to 4) i 2 c note stops operation serial interface uart0, uart1 stops operation a/d converter stops operation d/a converter stops operation external bus interface refer to chapter 5 bus control function . port function retains status before software stop mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the software stop mode was set. note pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only chapter 18 standby function user?s manual u15905ej2v1ud 466 18.5 securing oscillation stabilization time when the software stop mode is released, only the oscillation stabilization time set by the osts register elapses. if the software stop mode has been released by reset pin input, however, the reset value of the osts register, 2 19 /f x elapses. the timer for counting the oscillation stabilization time is sh ared with watchdog timer, so the oscillation stabilization time equal to the overflow time of the watchdog timer elapses. the following illustrates the operation performed when t he software stop mode is released by an interrupt request. figure 18-3. oscillation stabilization time oscillated waveform main clock oscillator stops oscillation stabilization time count main clock software stop mode status interrupt request caution for details of the osts register, refer to 10.3 (1) oscillation stabilization time selection register (osts). chapter 18 standby function user?s manual u15905ej2v1ud 467 18.6 subclock operation mode 18.6.1 setting and operation status the subclock operation mode is set when t he ck3 bit of the processor clock control register (pcc) is set to 1 in the normal operation mode. when the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. when the mck bit of the pcc register is set to 1, the operati on of the main clock oscillator is stopped. as a result, the system operates only with the subc lock. however, watchdog timer stops counting when subclock operation is started (cls bit of pcc register = 1). (watchdog time r retains the value before the subclock operation mode was set.) in the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. in addition, the power consumption can be further reduced to the level of the software stop mode by stopping the operation of the main system clock oscillator. table 18-8 shows the operation stat us in subclock operation mode. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits of the pcc register (using a bit manipulation instruction to manipulate the bit is reco mmended). for details of the pcc register, refer to 6.3 (1) processor clock control register (pcc). 18.6.2 releasing subc lock operation mode the subclock operation mode is released by reset pin i nput when the ck3 bit is cleared to 0. if the main clock is stopped (mck bit = 1), set the mck bit to 1, secure the oscilla tion stabilization time of the main clock by software, and clear the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, refer to 6. 3 (1) processor clock control register (pcc). chapter 18 standby function user?s manual u15905ej2v1ud 468 table 18-8. operation status in subclock operation mode operation status setting of subclock operation mode item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled cpu operable dma operable interrupt controller operable rom correction operable 16-bit timer/event counters (tm0, tm1) operable operable 8-bit timer/event counters (tm2 to tm5) operable operable real-time counter operable operable when f xt is selected as count clock watchdog timer stops operation csi0 to csi4 operable operable when sckn input clock is selected as operation clock (n = 0 to 4) i 2 c note operable stops operation serial interface uart0, uart1 operable stops operation a/d converter operable stops operation d/a converter operable operable (only when normal mode is selected) external bus interface operable port function settable internal data settable note pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only chapter 18 standby function user?s manual u15905ej2v1ud 469 18.7 sub-idle mode 18.7.1 setting and operation status the sub-idle mode is set when the psm bit of the power save mode register (psmr) is cleared to 0 and the stp bit of the power save control register (psc) is set to 1 in the subclock operation mode. in this mode, the clock oscillator c ontinues operation but clock supply to the cpu and the other on-chip peripheral functions is stopped. as a result, program execution is stopped and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and the other on-chip peripheral functions are stopped. however, the on-chip peripheral functions that can operate with the subclock or an extern al clock continue operating. because the sub-idle mode stops operat ion of the cpu and other on-chip per ipheral functions, it can reduce the power consumption more than the subclo ck operation mode. if the sub-idle mode is set after the main clock has been stopped, the power consumption c an be reduced to a level as low as that in the software stop mode. table 18-10 shows the operation status in the sub-idle mode. 18.7.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable interrup t request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), unm asked internal interrupt request from the peripheral functions operable in the sub-idle mode, or reset pin input. when the sub-idle mode is released by an interrupt reques t, the subclock operation mode is set. if it is released by reset pin input, the normal operation mode is restored. (1) releasing sub-idle m ode by non-maskable interrupt request or unmasked mas kable interrupt request the sub-idle mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt reques t. if the sub-idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the sub-idle mode is released, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than th at of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the sub-idle mode is released and that interrupt request is acknowledged. table 18-9. operation after releasing sub-idle mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed chapter 18 standby function user?s manual u15905ej2v1ud 470 (2) releasing sub-idle m ode by reset pin input the same operation as the normal reset operation is performed. table 18-10. operation status in sub-idle mode setting of sub-idle mode operation status item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled cpu stops operation dma stops operation interrupt controller stops operation rom correction stops operation 16-bit timer/event counters (tm0, tm1) stops operation 8-bit timer/event counters (tm2 to tm5) stops operation real-timer counter operable operable when f xt is selected as count clock watchdog timer stops operation csi0 to csi4 operable when sckn input clock is selected as operation clock (n = 0 to 4) i 2 c note 1 stops operation serial interface uart0, uart1 stops operation a/d converter stops operation d/a converter stops operation (output is retained) note 2 external bus interface refer to chapter 5 bus control function . port function retains status before sub-idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-idle mode was set. notes 1. pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y only 2. if the sub-idle mode is set immediately after t he d/a conversion has started (during conversion), the operation continues until the d/a conversion is comp leted, when the d/a conversion is completed, the output is retained. chapter 18 standby function user?s manual u15905ej2v1ud 471 18.8 control registers (1) power save control register (psc) this is an 8-bit register that controls the standby function. the stp bit of this register is used to specify the normal mode or idle/software stop mode. the psc register is a special register (refer to 3.4.8 special registers ). data can be written to this register only in a sp ecific sequence so that it s contents are not rewritten by mistake due to a program hang-up. this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. 0 psc 0 0 0 0 0 stp 0 normal mode idle/software stop mode stp 0 1 sets idle/software stop mode after reset: 00h r/w address: fffff1feh < > (2) power save mode register (psmr) this is an 8-bit register that cont rols the operation status and clock operation in the power save mode. this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. 0 idle mode software stop mode psm 0 1 specifies operation in software standby mode (valid when bit 1 (stp) of the psc register is set to 1) psmr 0 0 0 0 0 0 psm after reset: 00h r/w address: fffff820h < > cautions 1. be sure to clear bits 1 to 7 of the psmr register to 0. 2. the psm bit is valid only when the stp bit of the psc register is set to 1. (3) oscillation stabilization time selection register (osts) this is an 8-bit register that cont rols the operation status and clock operation in the power save mode. refer to 10.3 (1) oscillation stabilizatio n time selection register (osts) . user?s manual u15905ej2v1ud 472 chapter 19 reset function 19.1 overview the following reset functions are available. ? reset function by reset pin input ? reset function by wdt overflow (wdtres) if the reset pin goes high, the reset stat us is released, and the cp u starts executing the program. initialize the contents of each register in the program as necessary. the reset pin has a noise e liminator that operat es by analog delay to prevent malfunction caused by noise. 19.2 configuration figure 19-1. reset block diagram reset count clock analog delay circuit reset controller watchdog timer wdtres issued due to overflow reset signal to cpu reset signal to cg reset signal to other peripheral macros chapter 19 reset function user?s manual u15905ej2v1ud 473 19.3 operation the system is reset, initializing each hardware unit, when a low level is input to the reset pin by wdt overflow (wdtres). while a low level is bei ng input to the reset pi n, the main clock oscillator stops . therefore, the overall power consumption of the system can be reduced. if the reset pin goes high or if wdtres is received, the reset status is released. if the reset status is released by reset pin input, the o scillation stabilization time elapses (reset value of osts register: 2 19 /f x ) and then the cpu starts program execution. if the reset status is released by wdtres, the oscillati on stabilization time is not inserted because the main system clock oscillator does not stop. note reset by wdt overflow (wdtres) is valid only when the wdtm4 and wdtm3 bits of the watchdog timer mode register (wdtm) are set to ?11? (refer to 10.3 (3) ). chapter 19 reset function user?s manual u15905ej2v1ud 474 table 19-1. hardware status on reset pin input item during reset after reset main clock oscillator (f x ) oscillation stops (f x = 0 level). oscillation starts subclock oscillator (f xt ) oscillation can continue without effect from reset note 1 . peripheral clock (f xx to f xx /1024), internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts. however, operation stops during oscillation stabilization time count. wdt clock (f xw ) operation stops operation starts internal ram undefined if power-on reset occurs or writing data to ram and reset conflict (data loss). otherwise, retains values i mmediately before reset input. i/o lines (ports) high impedance on-chip peripheral i/o registers initialized to specified status real-time counter operation can be started note 2 other on-chip peripheral functions oper ation stops operation can be started notes 1. the on-chip feedback resistor is ?connected? by default (refer to 6.3 (1) processor clock control register (pcc) ). 2. the real-time counter performs a count operation on the subclock when the reset signal is input. if a clock resulting from dividing the main clock (f x ) by the baud rate generator (f brg ) is used as the count clock, the count clock is changed to the subclock (f xt ). table 19-2. hardware status on occurrence of wdtres item during reset after reset main clock oscillator (f x ) oscillation continues note 1 subclock oscillator (f xt ) oscillation can continue without effect from reset note 1 . peripheral clock (f xx to f xx /1024), internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts wdt clock (f xw ) operation continues internal ram undefined if writing data to ram and reset conflict (data loss). otherwise, retains values i mmediately before reset input. i/o lines (ports) high impedance on-chip peripheral i/o registers initialized to specified status real-time counter operation continues note 2 other on-chip peripheral functions oper ation stops operation can be started notes 1. the on-chip feedback resistor is ?connected? by default (refer to 6.3 (1) processor clock control register (pcc) ). 2. the real-time counter performs a count operation on the subclock when the reset signal is input. if a clock resulting from dividing the main clock (f x ) by the baud rate generator (f brg ) is used as the count clock, the count clock is changed to the subclock (f xt ). chapter 19 reset function user?s manual u15905ej2v1ud 475 figure 19-2. hardware status on reset input oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay figure 19-3. operation on power application oscillation stabilization time count must be 2 s or longer. initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal reset f x v dd f clk analog delay user?s manual u15905ej2v1ud 476 chapter 20 rom correction function 20.1 overview the rom correction function is used to replace part of t he program in the internal rom with the program of an external ram or the internal ram. by using this function, instruction bugs found in t he internal rom can be corrected at up to four places. figure 20-1. block diagram of rom correction instruction address bus block replaced by dbtrap instruction instruction data bus rom dbtrap instruction generation block correction address register n (coradn) correction control register (corenn bit) comparator remark n = 0 to 3 chapter 20 rom correction function user?s manual u15905ej2v1ud 477 20.2 control registers 20.2.1 correction address register s 0 to 3 (corad0 to corad3) these registers are used to set the first address (correction address) of the instruction to be corrected in the rom. the program can be corrected at up to four places be cause four correction address registers (coradn) are provided (n = 0 to 3). the coradn register can be read or written in 32-bit units. if the higher 16 bits of the coradn register are used as the coradnh regi ster, and the lower 16 bits as the coradnl register, these registers can be read or written in 16-bit units. set correction addresses within the range of 0000000h to 003fffeh. fix bits 0 and 18 to 31 note to 0. these registers are cleared to 00000000h after reset. note fix bits 0 and 17 to 31 to 0 in the pd703200 and 703200y. correction address fixed to 0 note 0 coradn (n = 0 to 3) after reset: 00000000h r/w address: corad0: fffff840h corad2: fffff848h corad1: fffff844h corad3: fffff84ch 1817 note bits 17 to 31 in the pd703200 and 703200y. chapter 20 rom correction function user?s manual u15905ej2v1ud 478 20.2.2 correction control register (corcn) this register disables or enables the correction operation of correction address register n (coradn) (n = 0 to 3). each channel can be enabled or disabled by this register. this register can be read or written in 8-bit or 1-bit units. this register is cleared to 00h after reset. 0 disabled enabled corenn 0 1 enables/disables correction operation corcn 0 0 0 coren3 coren2 coren1 coren0 after reset: 00h r/w address: fffff880h 3210 remark n = 0 to 3 table 20-1. correspondence between corcn register bits and coradn registers corcn register bit corresponding coradn register coren3 corad3 coren2 corad2 coren1 corad1 coren0 corad0 20.3 rom correction operation and program flow <1> if the address to be corrected and the fetch address of the internal rom match, the fetch code is replaced by the dbtrap instruction. <2> when the dbtrap instruction is executed , execution branches to address 00000060h. <3> software processing after branching causes the resu lt of rom correction to be judged (the fetch address and rom correction operation are confirmed) and exec ution to branch to the correction software. <4> after the correction software has been executed, the re turn address is set, and return processing is started by the dbret instruction. cautions 1. the software that pe rforms <3> and <4> must be ex ecuted in the internal rom/ram. 2. develop the program so that the rom correct ion function is not used until data has been completely written to the corcn regist er that controls rom correction. 3. when setting an address to be corrected to the coradn register, clear the higher bits to 0 in accordance with the capacity of th e internal rom. before setti ng, make sure that the corcn register is 00h. 4. the rom correction function cannot be used to correct the data of the internal rom. it can only be used to correct instructi on codes. if rom correction is u sed to correct data, that data is replaced with the dbtrap instruction code. chapter 20 rom correction function user?s manual u15905ej2v1ud 479 figure 20-2. rom correction operation and program flow reset & start fetch address = coradn coradn = dbpc-2? corenn = 1 dbtrap instruction executed? initialize microcontroller set coradn register change fetch code to dbtrap instruction jump to rom correction judgment address jump to address of replacement program execute fetch code jump to address 60h execute correction code error processing execute dbret instruction write return address to dbpc. write value of psw to dbpsw as necessary. set corcn register yes yes yes yes no no no no : processing by user program : rom correction judgment read data for setting rom correction from external memory remark n = 0 to 3 user?s manual u15905ej2v1ud 480 chapter 21 flash memory the following products are the flash memory ve rsions of the v850es/sa2 and v850es/sa3. caution there are differences in the amount of noise tolerance a nd noise radiation between flash memory versions and mask rom versions. when considering changing from a flash memory version to a mask rom version during the process from experimental manufacturing to mass production, make sure to sufficiently evalua te commercial samples (c s) (not engineering samples (es)) of the mask rom versions. (1) v850es/sa2 pd70f3201, 70f3201y: 256 kb flash memory versions (2) v850es/sa3 pd70f3204, 70f3204y: 256 kb flash memory versions in the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock, the same as in the mask rom version. writing to flash memory can be performed with the memory mounted on the target system (on board). a dedicated flash programmer (such as pg-fp4) is connec ted to the target system to perform writing. the following can be considered as the development envir onment and the applications using a flash memory. software can be altered after the v850es/sa2 or v850es/sa3 is solder-mounted on the target system. small scale production of various models is made easier by differentiating software. data adjustment in starting mass production is made easier. chapter 21 flash memory user?s manual u15905ej2v1ud 481 21.1 features erasure unit ? chip batch erase ? block erase blocks 0 to 3: 4 kb blocks 4 to 7: 60 kb erase/write method ? dedicated flash programmer mode (csi0, uart0, csi0 + hs) ? flash self programming mode support functions ? erase/write prohibit f unction (security function) other ? on-board rewrite ? erase/write with a single power supply ? interrupt acknowledgment during self programming 21.1.1 erasure unit the erasure units for 256 kb flash memory versions are shown below. (1) chip erase the area of xx000000 h to xx03ffffh can be erased at the same time. (2) block erase erasure can be performed in block units (60 kb 4, 4 kb 4). block 0: 4 kb block 1: 4 kb block 2: 4 kb block 3: 4 kb block 4: 60 kb block 5: 60 kb block 6: 60 kb block 7: 60 kb chapter 21 flash memory user?s manual u15905ej2v1ud 482 21.2 functional overview the on-chip flash memory of the v850es/sa2 and v850es/ sa3 can be rewritten using the rewriting functions of the dedicated flash programmer (on-b oard/off-board programming), regardless of whether or not the v850es/sa2 or v850es/sa3 has been mounted in the target system. the v850es/sa2 and v850es/sa3 support a security function that prohibits rewriting user programs written to the on-chip flash memory, thus protecting the program from being modified by unauthorized parties. the user-program based rewrite function (self programming) is a rewrite met hod suited to applications that assume program modifications after manufacturing and shipment of the target system, enabling rewr iting under any conditions because interrupt servicing during self programming is supported. table 21-1. rewrite methods rewrite method function operating mode on-board programming rewriting flash memory is possible by us ing the dedicated flash programmer after the v850es/sa2 or v850es/sa3 has been mounted on the target system off-board programming rewriting flash memory is possible by using the dedicated flash programmer and dedicated program adapter board (such as the fa series) before the v850es/sa2 or v850es/sa3 is mounted on the target system. flash memory programming mode self programming mode rewriting flash memory is possible note by executing a user program already written in the flash memory via on-board/off-board programming. normal operation mode note instruction fetch and data access is not possible from the on-board flash memory area during self programming, so the program for rewriting the internal ram or external memory must have been transferred and executed beforehand. remark the fa series is a product of naito densei machida mfg. co., ltd. table 21-2. basic functions support ( : supported/: not supported) function description on-board/off-board programming self programming block erase contents of specified block in memory are erased. chip erase all contents in memory are erased at once. writing writing to specified addresses and verify check are executed. verify/checksum data read from flash memory and data transferred from flash programmer are compared. note 1 blank check erasure status of entire memory is checked. security setting use of block erase command/chip erase command/program command is disabled . note 2 notes 1. reading is possible by user program. 2. the values set by on-board/off- board programming can only be retained. chapter 21 flash memory user?s manual u15905ej2v1ud 483 a list of security functions is shown below. t he block erase command prohibition/chip erase command prohibition/program command prohibition functions are enabled as the initial status after shipment; therefore, making security settings is possible only by setting while rewriting via on-board/off-board programming using the dedicated flash programmer. security settings can be used in combination. table 21-3. list of security functions rewrite operation when prohibited function description on-board/off-board programming self programming block erase command: chip erase command: block erase command prohibition executing the block erase command to all blocks is prohibited. the prohibition se tting can be initialized by executing the chip erase command. program command: block erase command: chip erase command: chip erase command prohibition executing block erasure on all blocks and the chip erase command is prohibited. once this prohibition function is set, the chip erase command cannot be executed, so no prohibition function can be initialized. program command: block erase command: chip erase command: program command prohibition executing a write command to all blocks and the block erase command is prohibited. the prohibition setting can be initialized by executing the chip erase command. program command: rewriting is possible regardless of prohibition settings. remark : can be executed : cannot be executed chapter 21 flash memory user?s manual u15905ej2v1ud 484 figure 21-1. wiring example of v850es/ sa2 flash write adap ter (fa-100gc-8eu-a) pd70f3201, pd70f3201y rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 si so sck /reset v pp reserve/hs clkout vdd2 vdd gnd gnd vdd vdd2 gnd vdd vdd2 vdd2 vdd gnd 1 5 10 15 20 25 75 70 65 60 55 51 26 30 35 40 45 50 100 95 90 85 80 76 connect to gnd. connect to v dd . remarks 1. handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.4 types of pin i/o circuits, i/o buffer power supplies, and connection of unused pins ). when connecting to v dd via a resistor, use of a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for a 100-pin plastic lqfp package. 3 . this diagram shows the wiring when using a handshake-supporting csi. chapter 21 flash memory user?s manual u15905ej2v1ud 485 table 21-4. wiring of v850es/sa2 fl ash write adapter (fa-100gc-8eu-a) pin configuration of flash programmer (pg-fp4) with csi0 + hs with csi0 with uart0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal p41/so0/sda 78 p41/so0/sda 78 p31/so1/txd0 9 so/txd output transmit signal p40/si0 77 p40/si0 77 p30/si1/rxd0 8 sck output transfer clock p42/sck0/ scl 79 p42/sck0/ scl 79 not needed not needed clkout output clock to v850es/sa2 x1 13 x1 13 x1 13 /reset output reset signal reset 15 reset 15 reset 15 flmd0 input write voltage flmd0 62 flmd0 62 flmd0 62 flmd1 input write voltage pld5/ad5/ flmd1 57 pld5/ad5/ flmd1 57 pld5/ad5/ flmd1 57 hs input handshake signal for csi0 + hs pdh0/a16 71 not needed not needed not needed not needed v dd 11, 19 v dd 11, 19 v dd 11, 19 av dd 2 av dd 2 av dd 2 vdd ? vdd voltage generation/ voltage monitor ev dd 37, 64 ev dd 37, 64 ev dd 37, 64 v ss 12, 18 v ss 12, 18 v ss 12, 18 av ss 3 av ss 3 av ss 3 av ref0 1 av ref0 1 av ref0 1 av ref1 6 av ref1 6 av ref1 6 gnd ? ground ev ss 36, 63 ev ss 36, 63 ev ss 36, 63 chapter 21 flash memory user?s manual u15905ej2v1ud 486 figure 21-2. wiring example of v850es/sa 3 flash write adapter (fa-121f1-ea6-a) pd70f3204, pd70f3204y rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 si so sck /reset v pp reserve/hs clkout vdd2 vdd gnd gnd vdd vdd2 gnd vdd vdd2 vdd2 vdd gnd h2 f2 g1 l6 m5 h1 b1 b2 a12 b12 g11 d11 g13 h12 j11 b11 c2 f1 f3 d2 connect to gnd. connect to v dd . remarks 1. handle the pins not described above in accord ance with the specified handling of unused pins (refer to 2.4 types of pin i/o circuits, i/o buffer power supplies, and connection of unused pins ). when connecting to v dd via a resistor, use of a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for a 121-pin plastic fbga package. 3 . this diagram shows the wiring when using a handshake-supporting csi. chapter 21 flash memory user?s manual u15905ej2v1ud 487 table 21-5. wiring of v850es/sa3 fl ash write adapter (fa-121f1-ea6-a) pin configuration of flash programmer (pg-fp3/pg-fp4) with csi0 + hs with csi0 with uart0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal p41/so0/sda a12 p41/so0/sda a12 p31/so1/txd0 e2 so/txd output transmit signal p40/si0 b12 p40/si0 b12 p30/si1/rxd0 e1 sck output transfer clock p42/sck0/ scl b11 p42/sck0/ scl b11 not needed not needed clk output clock to v850es/sa3 x1 f2 x1 f2 x1 f2 /reset output reset signal reset g1 reset g1 reset g1 flmd0 output write voltage flmd0 h12 flmd0 h12 flmd0 h12 flmd1 output write voltage pdl5/ad5/ flmd1 j11 pdl5/ad5/ flmd1 j11 pdl5/ad5/ flmd1 j11 hs input handshake signal for csi0 + hs pdh0/a16 d11 not needed not needed not needed not needed v dd f3, h2 v dd f3, h2 v dd f3, h2 av dd b1 av dd b1 av dd b1 vdd ? vdd voltage generation/ voltage monitor ev dd g13, l6 ev dd g13, l6 ev dd g13, l6 v ss f1, h1 v ss f1, h1 v ss f1, h1 av ss c2 av ss c2 av ss c2 av ref0 b2 av ref0 b2 av ref0 b2 av ref1 d2 av ref1 d2 av ref1 d2 gnd ? ground ev ss g11, m5 ev ss g11, m5 ev ss g11, m5 21.3 programming environment the following shows the environment r equired for writing programs to t he flash memory of v850es/sa2 and v850es/sa3. figure 21-3. environment required for writing programs to flash memory rs-232c dedicated flash programmer v850es/sa2, v850es/sa3 flmd0, flmd1 v dd v ss reset uart0/csi0 host machine pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y xxx x x xx x x xx xx xx x x x x y y yy statve a host machine is required for controlling the dedicated flash programmer. uart0 or csi0 is used for the interface between t he dedicated flash programmer and the v850es/sa2 or v850es/sa3 to perform writing, erasing, etc. a dedicated program adapter (fa series) required for off-board writing. chapter 21 flash memory user?s manual u15905ej2v1ud 488 21.4 communication mode the communication between the dedicated flash program mer and the v850es/sa2 or v850es/sa3 is performed by serial communication using uart0 or csi0 of the v850es/sa2, v850es/sa3. (1) uart0 transfer rate: 9,600 to 153,600 bps figure 21-4. communication with dedicated flash programmer (uart0) dedicated flash programmer v850es/sa2, v850es/sa3 v dd v ss reset txd0 rxd0 flmd0, flmd1 flmd0, flmd1 v dd gnd reset rxd txd pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x xxxx xxxxxx xxxx x x x x y y y y statve (2) csi0 serial clock: 2.4 khz to 2.5 mhz (msb first) figure 21-5. communication with de dicated flash programmer (csi0) dedicated flash programmer v850es/sa2, v850es/sa3 flmd0, flmd1 v dd v ss reset so0 si0 sck0 flmd0, flmd1 v dd gnd reset si so sck pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xxxxxx xxxx xxxx yyyy statve chapter 21 flash memory user?s manual u15905ej2v1ud 489 (3) csi0 + hs serial clock: 2.4 khz to 2.5 mhz (msb first) figure 21-6. communication with dedicated flash programmer (csi0 + hs) dedicated flash programmer v850es/sa2, v850es/sa3 v dd v ss reset so0 si0 sck0 pdh0 v dd flmd0, flmd1 flmd0, flmd1 gnd reset si so sck hs pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y yy xxxxx x xxxxx xxxx xx xx y yy y statve the dedicated flash programmer outputs the transfer clock, and the v850es/sa2 and v850es/sa3 operate as slaves. when the pg-fp4 is used as the d edicated flash programmer, it gener ates the following signals to the v850es/sa2 or v850es/sa3. for deta ils, refer to the pg-fp4 manual. table 21-6. signal generation of de dicated flash programmer (pg-fp4) pg-fp4 v850es/sa2, v850es/sa3 connection handling signal name i/o pin function pin name csi0 uart0 csi0 + hs flmd0 output mode setting, writing enable/ disable flmd0 flmd1 output mode setting flmd1 note 1 note 1 note 1 v dd i/o v dd voltage generation/ voltage monitoring v dd note 2 note 2 note 2 gnd ? ground v ss clk output clock output to v850es/sa2, v850es/sa3 x1 note 3 note 3 note 3 reset output reset signal reset si/rxd input receive signal so0/txd0 so/txd output transmit signal si0/rxd0 sck output transfer clock sck0 hs input handshake signal of csi0 + hs pdh0 notes 1. wire as shown in figures 21-1 and 21-2, or conn ect to gnd via a pull-down resistor on-board. 2. connect when power is supplied from the pg-fp4. 3. connect when the clock is supplied from the pg-f p4 (wire as shown in figures 21-1 and 21-2, or generate an oscillator on-board to supply the clock). remark : always connected : does not need to be connected chapter 21 flash memory user?s manual u15905ej2v1ud 490 21.5 pin connection when performing on-board writing, mount a connector on t he target system to connect to the dedicated flash programmer. also, incorporate a function on-board to s witch from the normal operation mode to the flash memory programming mode. when switched to the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. therefore, all the ports ente r the output high-impedance status, so that pin handling is requi red when the external device does no t acknowledge the output high-impedance status. 21.5.1 flmd0 pin in the normal operation mode, 0 v is input to the flmd 0 pin. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. the follow ing shows an example of the c onnection of the flmd0 pin. figure 21-7. flmd0 pin connection example v850es/sa2, v850es/sa3 flmd0 dedicated flash programmer connection pin pull-down resistor (r flmd0 ) chapter 21 flash memory user?s manual u15905ej2v1ud 491 21.5.2 flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v mu st be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 21-8. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/sa2, v850es/sa3 caution if the v dd signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal. table 21-7. operation mode according to flmd0 and flmd1 pin settings flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited 21.5.3 serial interface pin the following shows the pins used by each serial interface. table 21-8. pins used by serial interfaces serial interface pins used csi0 so0, si0, sck0 csi0 + hs so0, si0, sck0, pdh0 uart0 txd0, rxd0 when connecting a dedicated flash programmer to a serial interface pin that is connected to another device on- board, care should be taken to avoid conflict of signals and malfunction of the other device. chapter 21 flash memory user?s manual u15905ej2v1ud 492 (1) conflict of signals when the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other devi ce to the output high-impedance status. figure 21-9. conflict of signals (serial interface input pin) v850es/sa2, v850es/sa3 input pin conflict of signals dedicated flash programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side. chapter 21 flash memory user?s manual u15905ej2v1ud 493 (2) malfunction of other device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (i nput), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to t he other device or make the setting so that the input signal to the other device is ignored. figure 21-10. malfunction of other device v850es/sa2, v850es/sa3 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850es/sa2 or v850es/sa3 outputs affects the other device, isolate the signal on the other device side. v850es/sa2, v850es/sa3 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. chapter 21 flash memory user?s manual u15905ej2v1ud 494 21.5.4 reset pin when the reset signals of the dedicated flash programmer are connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of signal s, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 21-11. conflict of signals (reset pin) v850es/sa2, v850es/sa3 reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. 21.5.5 port pins (including nmi) when the flash memory programming mode is set, all the port pins except the pins that communicate with the dedicated flash programmer enter the output high-impedanc e status. if problems such as disabling output high- impedance status should occur in the external devices connected to the port, connect the port pins to v dd or v ss via resistors. 21.5.6 other signal pins connect x1, x2, xt1, xt2, av ref0 , and av ref1 to the same status as that in the normal operation mode. 21.5.7 power supply supply the same power (v dd , v ss , ev dd , ev ss , av dd , av ss ) as in normal operation mode. chapter 21 flash memory user?s manual u15905ej2v1ud 495 21.6 programming method 21.6.1 flash memory control the following shows the procedure for manipulating the flash memory. figure 21-12. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supplies flmd0 pulse no end switch to flash memory programming mode chapter 21 flash memory user?s manual u15905ej2v1ud 496 21.6.2 flash memory programming mode when rewriting the contents of flas h memory using the dedicated flash programmer, set the v850es/sa2 or v850es/sa3 to the flash memory programming mode. when switching modes, set the flmd0 and flmd1 pins before releasing reset. when performing on-board writing, cha nge modes using a jumper, etc. figure 21-13. flash memory programming mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxd0 (input) txd0 (output) 0 v v dd 0 v v dd 0 v v dd 0 v v dd 0 v v dd 0 v (note) power on oscillation stabilized communication mode selected flash control command communication (erase, write, etc.) reset cleared note the number of clocks to be inserted differs depending on the communication mode. for details, refer to table 21-9 . chapter 21 flash memory user?s manual u15905ej2v1ud 497 21.6.3 selection of communication mode in the v850es/sa2 and v850es/sa3, the communication mode is selected by inputting pulses (16 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the flmd0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. table 21-9. list of communication modes flmd0 pulse communication mode remarks 0 csi0 v850es/sa2 and v850es/sa3 perform slave operation, msb first 3 csi0 + hs v850es/sa2 and v850es/sa3 perform slave operation, msb first 8 uart0 communication rate: 9,600 bps (at reset), lsb first others rfu setting prohibited caution when uart is selected, th e receive clock is calculated based on the reset command sent from the dedicated flash programmer a fter receiving the flmd0 pulse. 21.6.4 communication command the v850es/sa2 and v850es/sa3 communicate with the de dicated flash programmer by means of commands. the command sent from the dedicated flash programmer to the v850es/sa2 or v850es/sa3 is called a ?command?. the response signal sent from the v850es/sa2 or v8 50es/sa3 to the dedicated flash programmer is called a ?response command?. figure 21-14. communication command dedicated flash programmer v850es/sa2, v850es/sa3 command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x xx x xxx xx x xx x x x x x x y y y y statve chapter 21 flash memory user?s manual u15905ej2v1ud 498 the following shows the commands for flash memory cont rol of the v850es/sa2 and v850es/sa3. all of these commands are issued from the dedicated flash progr ammer, and the v850es/sa2 and v850es/sa3 perform the various processing corresponding to the commands. table 21-10. flash memory control command support category command name csi0 csi0 + hs uart0 function blank check block blank check command checks the erase state of the entire memory. chip erase command erases the contents of the entire memory. erase block erase command erases the contents of the specified block memory. write write command writes data according to the specification of the write address and the number of bytes to be written, and executes a verify check. verify verify command compares the contents of the entire memory and the input data. reset command escapes from each state. oscillating frequency setting command sets the oscillation frequency. baud rate setting command ? ? sets the baud rate when using uart. silicon signature command reads the silicon signature information. version acquisition command reads the version information of the device. status command ? acquires the operation status. system setting and control security setting command erases chip and blocks, and sets security of write. chapter 21 flash memory user?s manual u15905ej2v1ud 499 21.7 rewriting by self programming 21.7.1 overview the v850es/sa2 and v850es/sa3 support a flash macro serv ice that allows the internal flash memory to be rewritten by the user program itself. by using this interf ace and a self programming library that is used to rewrite the flash memory via a user application program, the flash memo ry can be rewritten by a user application transferred in advance to the internal ram or external memory. c onsequently, the user program can be upgraded and constant data can be rewritten in the field. figure 21-15. concept of self programming flash memory erase, write flash macro service flash information flash function execution self programming library application program chapter 21 flash memory user?s manual u15905ej2v1ud 500 21.7.2 features (1) interrupt support instructions cannot be fetched from the flash memory during self programming. conv entionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. with the v850es/sa2 and v850es/sa3, however, a user handler can be registered to an entry ram area by using a library function, so that interrupt servicing can be perfo rmed by internal ram or external memory execution. (2) standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. if a security setting is not performed, flash information setting processing does not have to be executed. figure 21-16. standard self programming flow yes no flash memory manipulation ? disable accessing flash area ? disable setting of software stop mode ? disable stopping clock end of processing flash environment end processing internal verify processing all blocks finished? flash information setting processing write processing erase processing flash environment initialization processing chapter 21 flash memory user?s manual u15905ej2v1ud 501 (3) flash functions table 21-12. flash function list function name description support flashenv initialization of flash control macro flashblockerase erasure of only specified block flashwordwrite writing from specified address flashblockiverify internal veri fication of specified block flashblockblankcheck blank ch eck of specified block flashflmdcheck check of flmd pin flashstatuscheck status check of oper ation specified immediately before flashgetinfo reading of flash information flashsetinfo setting of flash information flashbootswap swapping of boot area flashsetuserhandler user interrupt handler registration function remark : supported : not supported (4) pin processing (a) flmd0 pin keep the voltage applied to the flmd0 pin at 0 v after reset release and while normal operation is performed. keep the voltage of the flmd0 pin at the ev dd level voltage only in the self programming mode (the voltage must be stabilized during self programmi ng). when self programming has been completed, the voltage of the flmd0 pin must be returned to 0 v. figure 21-17. mode switch timing ev dd 0 v ev dd 0 v normal operation mode normal operation mode self programming mode reset signal flmd0 pin chapter 21 flash memory user?s manual u15905ej2v1ud 502 (5) internal resources used the following table lists the internal resources used fo r self programming. these internal resources can also be used freely for purposes other than self programming. table 21-13. internal resources used resource name description entry ram area (124 bytes in either internal ram or external ram) routines and parameters used for the flash macro service are located in this area. the entry program and default parameters are copied by ca lling a library initialization function. stack area (user stack + 300 bytes) an extension of the stack used by the user is us ed by the library (can be used in both the internal ram and external ram). library code (1900 bytes) program entit y of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as user application. calls flash functions. maskable interrupt can be used in user application execution st atus or self programming status. to use this interrupt in the self programming status, the interrupt se rvicing start address must be registered in advance by a registration function. nmi interrupt can be used in user application execution stat us or self programming status. to use this interrupt in the self programming status, the interrupt se rvicing start address must be registered in advance by a registration function. user?s manual u15905ej2v1ud 503 chapter 22 electrical specifications absolute maximum ratings (t a = 25c, v ss = 0 v) parameter symbol conditions ratings unit v dd ? 0.5 to +3.5 v av dd ? 0.5 to +3.5 v ev dd ? 0.5 to +3.3 v av ss ? 0.5 to +0.5 v supply voltage ev ss ? 0.5 to +0.5 v input voltage v i other than x1, xt1, and port 7 ? 0.5 to ev dd + 0.3 note v v k x1 ? 0.5 to v dd + 0.3 note v clock input voltage v kt xt1 ? 0.5 to v dd + 0.3 note v analog input voltage v ian port 7 ? 0.5 to av dd + 0.3 note v analog reference voltage av ref av ref0 , av ref1 ? 0.5 to av dd + 0.3 note v per pin 4 ma output current, low i ol total for all pins 50 ma per pin ? 4 ma output current, high i oh total for all pins ? 50 ma output voltage v o v dd = 2.5 v 0.2 v ? 0.5 to v dd + 0.3 v note v normal operation mode ? 40 to +85 c operating ambient temperature t a flash programming mode ? 20 to +85 c storage temperature t stg ? 40 to +125 c note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output (or i/ o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins , however, can be directly connected to each other. direct connection of the output pins betw een an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. that is, the absolute maximu m ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolu te maximum ratings are not exceeded. the ratings and conditions indicated for dc ch aracteristics and ac char acteristics represent the quality assurance range during normal operation. chapter 22 electrical specifications user?s manual u15905ej2v1ud 504 capacitance (t a = 25c, v dd = av dd = ev dd = v ss = av ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 10 pf i/o capacitance c io 10 pf output capacitance c o f x = 1 mhz unmeasured pins returned to 0 v 10 pf operating conditions (v dd = av dd = ev dd ) parameter symbol conditions min. typ. max. unit @ v dd = 2.2 to 2.7 v, operation with main clock 0.0625 20 mhz internal system clock frequency f clk @ v dd = 2.2 to 2.7 v, operation with subclock 32 35 khz chapter 22 electrical specifications user?s manual u15905ej2v1ud 505 recommended oscillator (1) main clock oscillator (t a = ? 40 to +85c) (a) connection of ceramic res onator or crystal resonator x1 x2 parameter symbol conditions min. typ. max. unit oscillation frequency f x v dd = 2.2 to 2.7 v 2 20 mhz upon reset release 2 19 /f x s oscillation stabilization time upon stop mode release note s note the typ. value differs depending on the setting of the oscillation stabilization time select register (osts). caution ensure that the duty of the o scillation waveform is between 45% and 55%. remarks 1. connect the oscillator as close as possible to the x1 and x2 pins. 2. do not route the wiring near broken lines. 3. for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 22 electrical specifications user?s manual u15905ej2v1ud 506 (2) subclock oscillator (t a = ? 40 to +85c) (a) connection of crystal resonator xt1 xt2 parameter symbol conditions min. typ. max. unit oscillation frequency f xt 32 32.768 35 khz oscillation stabilization time 10 s caution ensure that the duty of the o scillation waveform is between 45% and 55%. remarks 1. connect the oscillator as close as possible to the xt1 and xt2 pins. 2. do not route the wiring near broken lines. 3. for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 22 electrical specifications user?s manual u15905ej2v1ud 507 dc characteristics (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v) (1/3) parameter symbol conditions min. typ. max. unit v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 0.8ev dd ev dd v v ih3 note 3 0.7av dd av dd v v ih4 x1 0.8v dd v dd v input voltage, high v ih5 xt1, xt2 0.8v dd v dd v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss 0.2ev dd v v il3 note 3 av ss 0.3av dd v v il4 x1 v ss 0.2v dd v input voltage, low v il5 xt1, xt2 v ss 0.2v dd v output voltage, high v oh1 note 4 i oh = ? 1 ma 0.7ev dd v v ol1 note 4 (except pins p40 and p42) i ol = 1.6 ma 0.4 v output voltage, low v ol2 p40, p42 i ol = 3 ma 0.4 v input leakage current, high i lih v in = v dd = ev dd 5 a input leakage current, low i lil v in = 0 v ? 5 a output leakage current, high i loh v o = v dd = ev dd 5 a output leakage current, low i lol v o = 0 v ? 5 a pull-up resistor r l v in = 0 v 10 30 100 k ? notes 1. p21, p31, p90, p91, p94 to p97, p99, p911, p 914, pcd1 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdh0 to pdh7, pdl0 to pdl15 (and their alternate-function pins) 2. reset, p00 to p05, p20, p22, p30, p32, p40 to p46, p92, p93, p98, p910, p912, p913, p915 (and their alternate-function pins) 3. p70 to p715, p80, p81 4. p00 to p05, p20 to p22, p30 to p32, p40 to p46, p90 to p915, pcd1 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdh0 to pdh7, pdl0 to pdl15 (and their alternate-function pins) chapter 22 electrical specifications user?s manual u15905ej2v1ud 508 dc characteristics (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v) (2/3) parameter symbol conditions min. typ. max. unit v dd = 2.2 to 2.7 v@2 to 20 mhz 0.8 f xx + 2.5 1.58 f xx + 6.0 ma f xx = 2 mhz 4.1 9.2 ma f xx = 4 mhz 5.7 12.3 ma f xx = 8 mhz 8.9 18.6 ma f xx = 10 mhz 10.5 21.8 ma f xx = 12 mhz 12.1 25.0 ma f xx = 17 mhz 16.1 31.9 ma i dd1 normal operation all peripheral functions operating f xx = 20 mhz 18.5 37.6 ma v dd = 2.2 to 2.7 v@2 to 20 mhz 0.37 f xx + 2.0 0.7 f xx + 3.0 ma f xx = 2 mhz 2.7 4.4 ma f xx = 4 mhz 3.5 5.8 ma f xx = 8 mhz 5.0 8.6 ma f xx = 10 mhz 6.2 10.0 ma f xx = 12 mhz 6.9 11.4 ma f xx = 17 mhz 8.2 14.9 ma i dd2 halt mode all peripheral functions operating f xx = 20 mhz 9.4 17.0 ma v dd = 2.2 to 2.7 v@2 to 20 mhz 40 f xx + 300 70 f xx + 500 a f xx = 2 mhz 380 640 a f xx = 4 mhz 460 780 a f xx = 8 mhz 620 1060 a f xx = 10 mhz 700 1200 a f xx = 12 mhz 780 1340 a f xx = 17 mhz 980 1690 a i dd3 idle mode rtc operation f xx = 20 mhz 1100 1900 a t a = 25 c 4 20 a sub oscillator, only rtc operates t a = 85 c ? 60 a t a = 25 c 1 10 a i dd4 stop mode sub oscillator stopped (xt1 = v ss ) t a = 85 c ? 50 a i dd5 subclock operation mode (f xt = 32.768 khz) 150 250 a t a = 25 c 4 20 a supply current note v850es/sa2 pd70f3201, pd70f3201y v850es/sa3 pd70f3204, pd70f3204y i dd6 sub-idle mode (f xt = 32.768 khz) main clock oscillator stopped, rtc operates t a = 85 c ? 60 a note the typical value of v dd is 2.5 v. the value does not include the current consumed at the output buffer. remark f xx : main clock frequency (mhz) chapter 22 electrical specifications user?s manual u15905ej2v1ud 509 dc characteristics (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v) (3/3) parameter symbol conditions min. typ. max. unit v dd = 2.2 to 2.7 v@2 to 20 mhz 0.7 f xx + 1.0 1.38 f xx + 1.5 ma f xx = 2 mhz 2.4 4.3 ma f xx = 4 mhz 3.8 7.0 ma f xx = 8 mhz 6.6 12.5 ma f xx = 10 mhz 8.0 15.3 ma f xx = 12 mhz 9.4 18.1 ma f xx = 17 mhz 12.9 25.0 ma i dd1 normal operation all peripheral functions operating f xx = 20 mhz 15.0 29.1 ma v dd = 2.2 to 2.7 v@2 to 20 mhz 0.36 f xx + 1.0 0.67 f xx + 1.5 ma f xx = 2 mhz 1.7 2.8 ma f xx = 4 mhz 2.4 4.2 ma f xx = 8 mhz 3.9 6.9 ma f xx = 10 mhz 4.6 8.2 ma f xx = 12 mhz 5.3 9.5 ma f xx = 17 mhz 7.1 12.9 ma i dd2 halt mode all peripheral functions operating f xx = 20 mhz 8.2 14.9 ma v dd = 2.2 to 2.7 v@2 to 20 mhz 40 f xx + 300 70 f xx + 500 a f xx = 2 mhz 380 640 a f xx = 4 mhz 460 780 a f xx = 8 mhz 620 1060 a f xx = 10 mhz 700 1200 a f xx = 12 mhz 780 1340 a f xx = 17 mhz 980 1690 a i dd3 idle mode rtc operation f xx = 20 mhz 1100 1900 a t a = 25 c 4 20 a sub oscillator, only rtc operates t a = 85 c ? 60 a t a = 25 c 1 10 a i dd4 stop mode sub oscillator stopped (xt1 = v ss ) t a = 85 c ? 50 a i dd5 subclock operation mode (f xt = 32.768 khz) 40 100 a t a = 25 c 4 20 a supply current note v850es/sa2 pd703200, pd703200y pd703201, pd703201y v850es/sa3 pd703204, pd703204y i dd6 sub-idle mode (f xt = 32.768 khz) main clock oscillator stopped, rtc operates t a = 85 c ? 60 a note the typical value of v dd is 2.5 v. the value does not include the current consumed at the output buffer. remark f xx : main clock frequency (mhz) chapter 22 electrical specifications user?s manual u15905ej2v1ud 510 data retention characteristics (1) in stop mode (t a = ? 40 to +85c, v ss = av ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr1 stop mode 1.5 2.7 v data retention current i dddr1 v dd = av dd = ev dd = v dddr1 1 60 a supply voltage rise time t rvd1 200 s supply voltage fall time t fvd1 200 s supply voltage hold time (from stop mode setting) t hvd1 0 ms stop release signal input time t drel1 0 ms data retention high-level input voltage v ihdr1 all input ports v ihn v dddr1 v data retention low-level input voltage v ildr1 all input ports 0 v iln v remark n = 1 to 5 v dd setting stop mode reset (input) nmi, intp0 to intp6 (input) nmi, intp0 to intp6 (input) (when stop mode is released at rising edge) t hvd1 t fvd1 t rvd1 t drel1 v dddr1 v ihdr1 v ildr1 v ihdr1 caution shifting to stop mode and restori ng from stop mode must be performed at v dd = 2.2 v min. (f clk = 20 mhz). chapter 22 electrical specifications user?s manual u15905ej2v1ud 511 ac characteristics ac test input measurement points (v dd , av dd , ev dd ) v dd 0 v v ih v il v ih v il measurement points ac test output measurement points v oh v ol v oh v ol measurement points load conditions dut (device under test) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, reduce the load capacitance of the device to 50 pf or less by in serting a buffer or by some other means. chapter 22 electrical specifications user?s manual u15905ej2v1ud 512 clock timing (1) operating conditions (t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit x1 input cycle t cyx <1> 50 500 ns x1 input high-level width t wxh <2> 25 250 ns x1 input low-level width t wxl <3> 25 250 ns x1 input rise time t xr <4> 0.5(t cyx ? t wxh ? t wxl ) ns x1 input fall time t xf <5> 0.5(t cyx ? t wxh ? t wxl ) ns clkout output cycle t cyk <6> 50 ns 16 s clkout high-level width t wkh <7> t cyk /2 ? 5 ns clkout low-level width t wkl <8> t cyk /2 ? 5 ns clkout rise time t kr <9> 5 ns clkout fall time t kf <10> 5 ns remark ensure that the duty of the oscillation waveform is between 45% and 55%. <1> <2> <4> <6> <7> <9> <10> <8> <5> <3> x1 (input) clkout (output) timing of output signal (excl uding external bus interface) (t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output rise time t or <11> 20 ns output fall time t of <12> 20 ns <11> <12> output signal chapter 22 electrical specifications user?s manual u15905ej2v1ud 513 bus timing (1) multiplexed bus mode (a) clkout asynchronous: in multiplexed bus mode (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <13> 0.5t ? 20 ns address hold time (from astb ) t hsta <14> 0.5t ? 15 ns delay time from rd to address float t frda <15> 2 ns data input setup time from address t said <16> (2 + n)t ? 30 ns data input setup time from rd t srid <17> (1 + n)t ? 25 ns delay time from astb to rd , wrm t dstrdwr <18> 0.5t ? 15 ns data input hold time (from rd ) t hrdid <19> 0 ns address output time from rd t drda <20> (1 + i)t ? 15 ns delay time from rd, wrm to astb t drdwrst <21> 0.5t ? 15 ns delay time from rd to astb t drdst <22> (1.5 + i)t ? 15 ns rd, wrm low-level width t wrdwrl <23> (1 + n)t ? 15 ns astb high-level width t wsth <24> t ? 15 ns data output time from wrm t dwrod <25> 15 ns data output setup time (to wrm ) t sodwr <26> (1 + n)t ? 20 ns data output hold time (from wrm ) t hwrod <27> t ? 15 ns t sawt1 <28> n 1 1.5t ? 30 ns wait setup time (to address) t sawt2 <29> n 1 (1.5 + n)t ? 30 ns t hawt1 <30> n 1 (0.5 + n)t ns wait hold time (from address) t hawt2 <31> n 1 (1.5 + n)t ns t sstwt1 <32> n 1 t ? 25 ns wait setup time (to astb ) t sstwt2 <33> n 1 (1 + n)t ? 25 ns t hstwt1 <34> n 1 nt ns wait hold time (from astb ) t hstwt2 <35> n 1 (1 + n)t ns hldrq high-level width t whqh <36> t + 10 ns hldak low-level width t whal <37> t ? 15 ns delay time from hldak to bus output t dhac <38> ? 3 ns delay time from hldrq to hldak t dhqha1 <39> (2n + 7.5)t + 25 ns delay time from hldrq to hldak t dhqha2 <40> 0.5t 1.5t + 25 ns remarks 1. t = 1/f cpu (f cpu : cpu operation clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. m = 0, 1 4. i: number of idle states insert ed after the read cycle (0 or 1). 5. the values in the above specificat ions are values for when clocks with a 1:1 duty ratio are input from x1. chapter 22 electrical specifications user?s manual u15905ej2v1ud 514 (b) clkout synchronous: in multiplexed bus mode (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka <41> 0 19 ns delay time from clkout to address float t fka <42> 0 19 ns delay time from clkout to astb t dkst <43> ? 5 14 ns delay time from clkout to rd, wrm t dkrdwr <44> ? 9 10 ns data input setup time (to clkout ) t sidk <45> 15 ns data input hold time (from clkout ) t hkid <46> 5 ns data output delay time from clkout t dkod <47> 19 ns wait setup time (to clkout ) t swtk <48> 20 ns wait hold time (from clkout ) t hkwt <49> 5 ns hldrq setup time (to clkout ) t shqk <50> 20 ns hldrq hold time (from clkout ) t hkhq <51> 5 ns delay time from clkout to bus float t dkf <52> 19 ns delay time from clkout to hldak t dkha <53> 19 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 22 electrical specifications user?s manual u15905ej2v1ud 515 read cycle (clkout synchr onous/asynchronous, 1 wait): in multiplexed bus mode clkout (output) a16 to a23 (output), a0 to a15 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 <41> <42> <43> <13> <44> <21> <20> <22> <18> <32> <48> <34> <33> <35> <28> <30> <29> <31> <49> <48> <49> <17> <23> <19> <43> <16> <45> <46> address hi-z <15> <44> <14> <24> remark wr0 and wr1 are high level. data chapter 22 electrical specifications user?s manual u15905ej2v1ud 516 write cycle (clkout synchronous /asynchronous, 1 wait): in multiplexed bus mode clkout (output) a16 to a23 (output), a0 to a15 (output) ad0 to ad15 (i/o) astb (output) wr0 (output), wr1 (output) wait (input) t1 t2 tw t3 <41> <47> <43> <13> <44> <21> <27> <18> <32> <48> <34> <33> <35> <28> <30> <29> <31> <49> <48> <49> <26> <23> <24> <14> <43> data address <25> <44> remark rd is high level. chapter 22 electrical specifications user?s manual u15905ej2v1ud 517 bus hold: in mult iplexed bus mode clkout (output) hldrq (input) hldak (output) a16 to a23 (output) a0 to a15 (output) ad0 to ad15 (i/o) astb (output) rd (output), wr0 (output), wr1 (output) <50> <51> <53> <38> <37> <39> <40> <50> <53> <36> th th th ti hi-z hi-z hi-z data hi-z <52> chapter 22 electrical specifications user?s manual u15905ej2v1ud 518 (2) in separate bus mode (a) read cycle (clkout asynchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to rd ) t sard <54> 0.5t ? 20 ns address hold time (from rd ) t hard <55> 0 ns rd low-level width t wrdl <56> (1.5 + n)t ? 10 ns data setup time (to rd ) t sisd <57> 20 ns data hold time (from rd ) t hisd <58> 0 ns data setup time (to address) t said <59> (2 + n)t ? 25 ns t srdwt1 <60> 0.5t ? 20 ns wait setup time (to rd ) t srdwt2 <61> (0.5 + n)t ? 20 ns t hrdwt1 <62> 0.5t ns wait hold time (from rd ) t hrdwt2 <63> (0.5 + n)t ns t sawt1 <64> t ? 30 ns wait setup time (to address) t sawt2 <65> (1 + n)t ? 30 ns t hawt1 <66> t ns wait hold time (from address) t hawt2 <67> (1 + n)t ns remarks 1. t = 1/f cpu (f cpu : cpu operation clock frequency) 2. n: number of wait clocks inserted in bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are the va lues for when clocks with a 1:1 duty ratio are input from x1. (b) read cycle (clkout synchronous ): in separate bus mode (t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <68> 0 19 ns data input setup time (to clkout ) t sisdk <69> 20 ns data input hold time (from clkout ) t hkisd <70> 5 ns delay time from clkout to rd t dksr <71> 0 19 ns wait setup time (to clkout ) t swtk <72> 20 ns wait hold time (from clkout ) t hkwt <73> 5 ns remark the values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from x1. chapter 22 electrical specifications user?s manual u15905ej2v1ud 519 (c) write cycle (clkout asynchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to wrm ) t saw <74> t ? 20 ns address hold time (from wrm ) t haw <75> 0.5t ? 10 ns wrm low-level width t wwrl <76> (0.5 + n)t ? 10 ns data output time from wrm t dosdw <77> ? 5 ns data setup time (to wrm ) t sosdw <78> (0.5 + n)t ? 15 ns data hold time (from wrm ) t hosdw <79> 0.5t ? 10 ns data setup time (to address) t saod <80> t ? 25 ns t swrwt1 <81> 20 ns wait setup time (to wrm ) t swrwt2 <82> nt ? 20 ns t hwrwt1 <83> 0 ns wait hold time (from wrm ) t hwrwt2 <84> nt ns t sawt1 <85> t ? 25 ns wait setup time (to address) t sawt2 <86> (1 + n)t ? 20 ns t hawt1 <87> t ns wait hold time (from address) t hawt2 <88> (1 + n)t ns remarks 1. m = 0, 1 2. t = 1/f cpu (f cpu : cpu operation clock frequency) 3. n: number of wait clocks inserted in bus cycle the sampling timing changes when a programmable wait is inserted. 4. the values in the above specifications are the va lues for when clocks with a 1:1 duty ratio are input from x1. (d) write cycle (clkout synchronous ): in separate bus mode (t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <89> 0 19 ns delay time from clkout to data output t dksd <90> 0 19 ns delay time from clkout to wrm t dksw <91> 0 19 ns wait setup time (to clkout ) t swtk <92> 20 ns wait hold time (from clkout ) t hkwt <93> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are the va lues for when clocks with a 1:1 duty ratio are input from x1. chapter 22 electrical specifications user?s manual u15905ej2v1ud 520 read cycle (clkout asynchronous, 1 wait): in separate bus mode clkout (output) t1 <59> hi-z hi-z <54> <56> <63> <61> <62> <60> <14> <66> <65> <67> <58> <57> <55> tw t2 rd (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) chapter 22 electrical specifications user?s manual u15905ej2v1ud 521 read cycle (clkout synchronous, 1 wait): in separate bus mode clkout (output) t1 <71> <72> <73> <72> <73> <68> <71> <69> <70> hi-z hi-z tw t2 rd (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) <68> chapter 22 electrical specifications user?s manual u15905ej2v1ud 522 write cycle (clkout asynchronous, 1 wait): in separate bus mode clkout (output) t1 <80> <74> <77> <76> <84> <82> <83> <81> <85> <87> <86> <88> <79> <78> <75> tw t2 wr0, wr1 (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) hi-z hi-z chapter 22 electrical specifications user?s manual u15905ej2v1ud 523 write cycle (clkout synchronous, 1 wait): in separate bus mode clkout (output) t1 <90> <91> <93> <92> 91> tw t2 wr0, wr1 (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) <89> <89> <93> <92> <90> hi-z hi-z chapter 22 electrical specifications user?s manual u15905ej2v1ud 524 reset/interrupt timing (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit at power-on, while erasing/writing flash memory 2 s reset low-level width t wrsl <95> other than above 500 ns nmi high-level width t wnih <96> 500 ns nmi low-level width t wnil <97> 500 ns intpn high-level width t with <98> n = 0 to 6 (analog noise elimination) 500 ns intpn low-level width t witl <99> n = 0 to 6 (analog noise elimination) 500 ns remark t = 1/f xx reset <95> reset (input) interrupt <96> <97> nmi (input) <98> <99> intpn (input) remark n = 0 to 6 chapter 22 electrical specifications user?s manual u15905ej2v1ud 525 timer timing (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit n = 0, 1 2t + 20 ns tin high-level width n = 2 to 5 40 ns n = 0, 1 2t + 20 ns tin low-level width n = 2 to 5 40 ns tclrn high-level width n = 0, 1 2t + 20 ns tclrn low-level width n = 0, 1 2t + 20 ns intpnm high-level width t with nm = 00, 01, 10, 11 2t + 20 ns intpnm low-level width t witl nm = 00, 01, 10, 11 2t + 20 ns remark t = 1/f xx chapter 22 electrical specifications user?s manual u15905ej2v1ud 526 csi timing (1) master mode (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle time t kcy1 <100> output 200 ns sckn high-/low-level width t kh1 <101> output t kcy1 /2 ? 10 ns sin setup time (to sckn ) t sik1 <102> 30 ns sin hold time (from sckn ) t ksi1 <103> 30 ns delay time from sckn to son output t kso1 <104> 30 ns remark n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) (2) slave mode (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle time t kcy2 <100> output 200 ns sckn high-/low-level width t kh2 <101> output 90 ns sin setup time (to sckn ) t sik2 <102> 50 ns sin hold time (from sckn ) t ksi2 <103> 50 ns delay time from sckn to son output t kso2 <104> 50 ns remark n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) <103> <104> <102> <100> <101> hi-z hi-z <101> remark n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) sckn (i/o) sin (input) son (output) input data output data chapter 22 electrical specifications user?s manual u15905ej2v1ud 527 i 2 c bus mode ( pd703200y, 703201y, 703204y, 70f3201y, 70f3204y only) (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v) normal mode high-speed mode parameter symbol min. max. min. max. unit scl clock frequency f clk 0 100 0 400 khz bus-free time (between stop/start conditions) t buf <105> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <106> 4.0 ? 0.6 ? s scl clock low-level width t low <107> 4.7 ? 1.3 ? s scl clock high-level width t high <108> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <109> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <110> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <111> 250 ? 100 note 4 ? ns sda and scl signal rise time t r <112> ? 1,000 20 + 0.1cb note 5 300 ns sda and scl signal fall time t f <113> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <114> 4.0 ? 0.6 ? s pulse width with spike suppressed by input filter t sp <115> ? ? 0 50 ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda signal (at v ihmin. . of scl signal) in order to occupy the undef ined area at the falling edge of scl. 3. if the system does not extend the scl signal low hold time (t low ), only the maximum data hold time (t hd:dat ) needs to be satisfied. 4. the high-speed-mode i 2 c bus can be used in a normal-mode i 2 c bus system. in this case, set the high- speed-mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl signal?s low state hold time: t su : dat 250 ns ? if the system extends the scl signal?s low state hold time: transmit the next data bit to the sda line prior to releasing the scl line (t rmax. + t su : dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark the maximum operating frequency of the pd703200y, 703201y, 703204y, 70f3201y, and 70f3204y is f xx = 17 mhz. chapter 22 electrical specifications user?s manual u15905ej2v1ud 528 i 2 c bus mode ( pd703200y, 703201y, 703204y, 70f3201y, 70f3204y only) stop condition stop condition start condition restart condition scl (i/o) sda (i/o) <107> <113> <113> <112> <112> <110> <111> <109> <106> <105> <106> <115> <114> <108> a/d converter (t a = ? 40 to +85c, v dd = av dd = av ref0 = 2.2 to 2.7 v, av ss = v ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1 0.1 0.3 %fsr conversion time t conv 6.3 150 s zero-scale error note 1 0.2 %fsr full-scale error note 1 0.2 %fsr integral linearity error note 2 2 lsb differential linearity error note 2 1 lsb analog reference voltage av ref av ref0 = av dd 2.2 2.7 v analog input voltage v ian av ss av ref v av ref0 current ai ref0 10 a av dd power supply current ai dd 400 800 a notes 1. excluding quantization error ( 0.05%fsr) 2. excluding quantization error ( 0.5 lsb) remark lsb: least significant bit fsr: full-scale range chapter 22 electrical specifications user?s manual u15905ej2v1ud 529 d/a converter (t a = ? 40 to +85 c, v dd = av dd = av ref1 = 2.2 to 2.7 v, av ss = v ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note load conditions: 2 m ? , 30 pf av ref1 = v dd 0.8 %fsr settling time 20 s output resistance 10 k ? analog reference voltage av ref av ref1 = v dd 2.2 2.7 v av ref1 current av ref1 per channel, during d/a operation 500 a note excluding quantization error ( 0.2%fsr). chapter 22 electrical specifications user?s manual u15905ej2v1ud 530 flash memory programming characteristics ( pd70f3201, 70f3201y, 70f32 04, and 70f3204y only) (1) basic characteristics (v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit operating frequency f xx 2.2 to 2.7 v 2 20 mhz supply voltage v dd 2.2 2.7 v number of rewrites c wrt note 100 times when writing 6 ma supply current i dd when erasing 6 ma programming temperature t prg 2.2 to 2.7 v ? 20 +85 c note when writing data for the first time to a shipped product, a product that can be ?erased then written? and a product that can be ?only written? can be both be rewritten once. example: p write, e: erase shipped product p e p e p: number of rewrites: 3 shipped product e p e p e p: number of rewrites: 3 (2) serial write operation characteristics (t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.2 to 2.7 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit set time from vdd to flmd0 t dp <116> 10 s _reset release time from flmd0 t pr <117> 2 s time from oscillation stabilization time end to flmd0 pulse output start t rp <118> f xx = 20 mhz 230 s flmd0 pulse high-/low-level width t pw <119> 10 100 s time from oscillation stabilization time end to flmd0 pulse input signal end t rpe <120> f xx = 20 mhz 100 ms time from oscillation stabilization time end to reset command input note 1 t rc <121> f xx = 20 mhz t rpe + 50 ms time from oscillation stabilization time end to low data input 1 note 2 t ri <122> f xx = 20 mhz t rpe + 50 ms time from low data input 1 to low data input 2 note 2 t i2 <123> f xx = 20 mhz 1 ms time from low data input 2 to reset command input 2 note 2 t 2c <124> f xx = 20 mhz 1 ms low data input width note 2 t l1 , t l2 <125> ?00h? @9600 bps notes 1. when csi0 or csi0 + hs is selected. 2. when uart0 is selected. chapter 22 electrical specifications user?s manual u15905ej2v1ud 531 v dd v dd 0 v v dd 0 v v dd 0 v v dd 0 v v dd 0 v reset flmd0 oscillation stabilization time flmd1 so/txd l <116> <117> <118> <119> <119> <120> <121>/<122> <125> <125> <123> <124> user?s manual u15905ej2v1ud 532 chapter 23 package drawings s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e 75 76 51 125 50 100 26 a3 s 0.17 + 0.03 ? 0.07 (unit:mm) item dimensions d e hd he a a1 a2 a3 b 14.00 0.20 14.00 0.20 16.00 0.20 16.00 0.20 1.20 max. 0.10 0.05 1.00 0.05 0.25 0.22 0.05 c e x y zd ze 0.50 0.08 0.08 1.00 1.00 l lp l1 0.50 0.60 0.15 1.00 0.20 p100gc-50-yeu 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 100-pin plastic tqfp (fine pitch) (14x14) chapter 23 package drawings user?s manual u15905ej2v1ud 533 121-pin plastic fbga (12x12) item millimeters d 12.00 0.10 e 12.00 0.10 0.10 p121f1-80-ea6 index mark a w 0.20 a2 a1 a 1.13 e 0.80 1.48 0.10 0.35 0.06 x y 0.20 y1 1.20 zd 1.20 ze 0.08 ze a2 a1 b zd b a s s wa s wb s y1 se y 13 12 11 10 9 8 7 6 5 4 3 2 1 nmlk jhgfedcba s xab m e d b 0.50 + 0.05 ? 0.10 user?s manual u15905ej2v1ud 534 chapter 24 recommended soldering conditions the v850es/sa2 and v850es/sa3 should be soldered and m ounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, consult an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 24-1. surface mounting type soldering conditions(1/2) (1) pd703201gc-xxx-yeu-a 100-pin plastic tqfp (fine pitch) (14 14) pd70f3201gc-yeu-a 100-pin plastic tqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 36 to 72 hours) ir60-363-3 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). remark products with -a at the end of the part number are lead-free products. (2) pd703201ygc-xxx-yeu-a 100-pin plastic tqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). remark products with -a at the end of the part number are lead-free products. chapter 24 recommended soldering conditions user?s manual u15905ej2v1ud 535 table 24-1. surface mounting type soldering conditions(2/2) (3) pd703204f1-xxx-ea6-a 121-pin plastic fbga (12 12) pd703204yf1-xxx-ea6-a 121-pin plastic fbga (12 12) pd70f3204f1-ea6-a 121-pin plastic fbga (12 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-203-3 note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). remark products with -a at the end of the part number are lead-free products. (4) pd703200gc-xxx-yeu-a 100-pin plastic tqfp (fine pitch) (14 14) pd703200ygc-xxx-yeu-a 100-pin plastic tqfp (fine pitch) (14 14) pd70f3201ygc-yeu-a 100-pin plastic tqfp (fine pitch) (14 14) pd70f3204yf1-ea6-a 121-pin plastic fbga (12 12) undefined user?s manual u15905ej2v1ud 536 appendix a register index (1/7) symbol name unit page adcr a/d conversion result register adc 286 adcrh a/d conversion result register h adc 286 adic interrupt control register intc 441 adm a/d converter mode register adc 282 ads analog input channel specification register adc 284 asif0 uart0 transmit status register uart 307 asif1 uart1 transmit status register uart 307 asim0 uart0 operation mode register uart 303 asim1 uart1 operation mode register uart 303 asis0 uart0 reception error status register uart 306 asis1 uart1 reception error status register uart 306 awc address wait control register bcu 191 bcc bus cycle control register bcu 192 brgc0 baud rate generator compare register 0 brg 325 brgc1 baud rate generator compare register 1 brg 325 brgic interrupt control register intc 441 bsc bus size configuration register bcu 181 cc00 capture/compare register 00 timer 215 cc01 capture/compare register 01 timer 215 cc10 capture/compare register 10 timer 215 cc11 capture/compare register 11 timer 215 ccic00 interrupt control register intc 441 ccic01 interrupt control register intc 441 ccic10 interrupt control register intc 441 ccic11 interrupt control register intc 441 cksr0 clock select register 0 brg 324 cksr1 clock select register 1 brg 324 corad0 correction address register 0 romc 477 corad0h correction address register 0h romc 477 corad0l correction address register 0l romc 477 corad1 correction address register 1 romc 477 corad1h correction address register 1h romc 477 corad1l correction address register 1l romc 477 corad2 correction address register 2 romc 477 corad2h correction address register 2h romc 477 corad2l correction address register 2l romc 477 corad3 correction address register 3 romc 477 corad3h correction address register 3h romc 477 corad3l correction address register 3l romc 477 appendix a register index user?s manual u15905ej2v1ud 537 (2/7) symbol name unit page corcn correction control register romc 478 cr2 compare register 2 timer 241 cr3 compare register 3 timer 241 cr4 compare register 4 timer 241 cr5 compare register 5 timer 241 csic0 clocked serial interface cl ock selection register 0 csi 338 csic1 clocked serial interface cl ock selection register 1 csi 338 csic2 clocked serial interface cl ock selection register 2 csi 338 csic3 clocked serial interface cl ock selection register 3 csi 338 csic4 clocked serial interface cl ock selection register 4 csi 338 csiic0 interrupt control register intc 441 csiic1 interrupt control register intc 441 csiic2 interrupt control register intc 441 csiic3 interrupt control register intc 441 csiic4 interrupt control register intc 441 csim0 clocked serial interf ace mode register 0 csi 336 csim1 clocked serial interf ace mode register 1 csi 336 csim2 clocked serial interf ace mode register 2 csi 336 csim3 clocked serial interf ace mode register 3 csi 336 csim4 clocked serial interf ace mode register 4 csi 336 ctbp callt base pointer cpu 61 ctpc callt execution status saving register cpu 60 ctpsw callt execution status saving register cpu 60 dacs0 d/a converter conversion value setting register 0 dac 296 dacs1 d/a converter conversion value setting register 1 dac 296 dadc0 dma addressing control register 0 dmac 413 dadc1 dma addressing control register 1 dmac 413 dadc2 dma addressing control register 2 dmac 413 dadc3 dma addressing control register 3 dmac 413 dam d/a converter mode register dac 295 day day count register rtc 264 dayb day count setting register rtc 264 dbc0 dma transfer count register 0 dmac 412 dbc1 dma transfer count register 1 dmac 412 dbc2 dma transfer count register 2 dmac 412 dbc3 dma transfer count register 3 dmac 412 dbpc exception/debug trap status saving register cpu 61 dbpsw exception/debug trap status saving register cpu 61 dchc0 dma channel control register 0 dmac 414 dchc1 dma channel control register 1 dmac 414 dchc2 dma channel control register 2 dmac 414 dchc3 dma channel control register 3 dmac 414 dda0h dma destination address register 0h dmac 411 dda0l dma destination address register 0l dmac 411 appendix a register index user?s manual u15905ej2v1ud 538 (3/7) symbol name unit page dda1h dma destination address register 1h dmac 411 dda1l dma destination address register 1l dmac 411 dda2h dma destination address register 2h dmac 411 dda2l dma destination address register 2l dmac 411 dda3h dma destination address register 3h dmac 411 dda3l dma destination address register 3l dmac 411 dmaic0 interrupt control register intc 441 dmaic1 interrupt control register intc 441 dmaic2 interrupt control register intc 441 dmaic3 interrupt control register intc 441 dsa0h dma source address register 0h dmac 410 dsa0l dma source address register 0l dmac 410 dsa1h dma source address register 1h dmac 410 dsa1l dma source address register 1l dmac 410 dsa2h dma source address register 2h dmac 410 dsa2l dma source address register 2l dmac 410 dsa3h dma source address register 3h dmac 410 dsa3l dma source address register 3l dmac 410 dtfr0 dma trigger factor register 0 dmac 415 dtfr1 dma trigger factor register 1 dmac 415 dtfr2 dma trigger factor register 2 dmac 415 dtfr3 dma trigger factor register 3 dmac 415 dwc0 data wait control register 0 bcu 188 ecr interrupt source register cpu 58 eipc interrupt status saving register cpu 57 eipsw interrupt status saving register cpu 57 eximc external bus interface mode control register bcu 180 fepc nmi status saving register cpu 58 fepsw nmi status saving register cpu 58 hour hour count register rtc 263 hourb hour count setting register rtc 264 iic iic shift register i 2 c 363 iicc iic control register i 2 c 353 iiccl iic clock select register i 2 c 361 iicic interrupt control register intc 441 iics iic status register i 2 c 358 iicx iic function expansion register i 2 c 362 imr0 interrupt mask register 0 intc 442 imr0h interrupt mask register 0h intc 442 imr0l interrupt mask register 0l intc 442 imr1 interrupt mask register 1 intc 442 imr1h interrupt mask register 1h intc 442 imr1l interrupt mask register 1l intc 442 imr2 interrupt mask register 2 intc 442 appendix a register index user?s manual u15905ej2v1ud 539 (4/7) symbol name unit page imr2l interrupt mask register 2l intc 442 intf0 external interrupt falling edge specification register 0 intc 95, 446 intf9 external interrupt falling edge specification register 9 intc 135, 447 intf9l external interrupt falling edge specification register 9l intc 135, 447 intr0 external interrupt rising edge specification register 0 intc 96, 446 intr9 external interrupt rising edge specification register 9 intc 136, 447 intr9l external interrupt rising edge specification register 9l intc 136, 447 ispr in-service priority register intc 443 min minute count register rtc 263 minb minute count setting register rtc 263 osts oscillation stabilization time selection register wdt 271, 276 ovfic0 interrupt control register intc 441 ovfic1 interrupt control register intc 441 p0 port register 0 port 93 p2 port register 2 port 100 p3 port register 3 port 107 p4 port register 4 port 114 p7 port register 7 port 124 p7h port register 7h port 124 p7l port register 7l port 124 p8 port register 8 port 125 p9 port register 9 port 128 p9h port register 9h port 128 p9l port register 9l port 128 pc program counter cpu 55 pcc processor clock control register cg 205 pcd port register cd port 144 pcm port register cm port 147 pcs port register cs port 153 pct port register ct port 158 pdh port register dh port 163 pdl port register dl port 167 pdlh port register dlh port 167 pdll port register dll port 167 pf2 port function register 2 port 101 pf3 port function register 3 port 109 pf4 port function register 4 port 117 pf9 port function register 9 port 134 pf9h port function register 9h port 134 pfc3 port function control register 3 port 108 pfc4 port function control register 4 port 116 pfc9 port function control register 9 port 132 pfc9h port function control register 9h port 132 pfc9l port function control register 9l port 132 appendix a register index user?s manual u15905ej2v1ud 540 (5/7) symbol name unit page pfm power fail comparison mode register adc 285 pft power fail comparison threshold value register adc 285 pic0 interrupt control register intc 441 pic1 interrupt control register intc 441 pic2 interrupt control register intc 441 pic3 interrupt control register intc 441 pic4 interrupt control register intc 441 pic5 interrupt control register intc 441 pic6 interrupt control register intc 441 pm0 port mode register 0 port 93 pm2 port mode register 2 port 100 pm3 port mode register 3 port 107 pm4 port mode register 4 port 114 pm9 port mode register 9 port 129 pm9h port mode register 9h port 129 pm9l port mode register 9l port 129 pmc0 port mode control register 0 port 94 pmc2 port mode control register 2 port 101 pmc3 port mode control register 3 port 108 pmc4 port mode control register 4 port 115 pmc9 port mode control register 9 port 130 pmc9h port mode control register 9h port 130 pmc9l port mode control register 9l port 130 pmccm port mode control register cm port 148 pmccs port mode control register cs port 154 pmcct port mode control register ct port 159 pmcd port mode register cd port 144 pmcdh port mode control register dh port 164 pmcdl port mode control register dl port 168 pmcdlh port mode control register dlh port 168 pmcdll port mode control register dll port 168 pmcm port mode register cm port 147 pmcs port mode register cs port 153 pmct port mode register ct port 158 pmdh port mode register dh port 163 pmdl port mode register dl port 168 pmdlh port mode register dlh port 168 pmdll port mode register dll port 168 prcmd command register cpu 85 prscm prescaler compare register cg 211 prsm prescaler mode register cg 210 psc power save control register cg 207, 471 psmr power save mode register cg 207, 471 psw program status word cpu 59 appendix a register index user?s manual u15905ej2v1ud 541 (6/7) symbol name unit page pu0 pull-up resistor option register 0 port 95 pu2 pull-up resistor option register 2 port 102 pu3 pull-up resistor option register 3 port 109 pu4 pull-up resistor option register 4 port 117 pu9 pull-up resistor option register 9 port 135 pu9h pull-up resistor option register 9h port 135 pu9l pull-up resistor option register 9l port 135 rovic interrupt control register intc 441 rtcc0 rtc operation control register 0 rtc 260 rtcc1 rtc operation control register 1 rtc 261 rtcic interrupt control register intc 441 rxb0 receive buffer register 0 uart 308 rxb1 receive buffer register 1 uart 308 sec second count register rtc 262 secb second count setting register rtc 262 ses0 valid edge select register 0 timer 221 ses1 valid edge select register 1 timer 221 sio0 serial i/o shift register 0 csi 340 sio1 serial i/o shift register 1 csi 340 sio2 serial i/o shift register 2 csi 340 sio3 serial i/o shift register 3 csi 340 sio4 serial i/o shift register 4 csi 340 sioe0 receive-only serial i/o shift register 0 csi 340 sioe1 receive-only serial i/o shift register 1 csi 340 sioe2 receive-only serial i/o shift register 2 csi 340 sioe3 receive-only serial i/o shift register 3 csi 340 sioe4 receive-only serial i/o shift register 4 csi 340 sotb0 clocked serial interface tr ansmit buffer register 0 csi 341 sotb1 clocked serial interface tr ansmit buffer register 1 csi 341 sotb2 clocked serial interface tr ansmit buffer register 2 csi 341 sotb3 clocked serial interface tr ansmit buffer register 3 csi 341 sotb4 clocked serial interface tr ansmit buffer register 4 csi 341 sreic0 interrupt control register intc 441 sreic1 interrupt control register intc 441 sric0 interrupt control register intc 441 sric1 interrupt control register intc 441 stic0 interrupt control register intc 441 stic1 interrupt control register intc 441 subc sub-count register rtc 262 sva slave address register i 2 c 363 sys system status register cpu 86 tcl2 timer clock selection register 2 timer 242 tcl3 timer clock selection register 3 timer 242 tcl4 timer clock selection register 4 timer 243 appendix a register index user?s manual u15905ej2v1ud 542 (7/7) symbol name unit page tcl5 timer clock selection register 5 timer 243 tm0 timer 0 timer 214 tm1 timer 1 timer 214 tm2 timer counter 2 timer 241 tm3 timer counter 3 timer 241 tm4 timer counter 4 timer 241 tm5 timer counter 5 timer 241 tmc00 timer control register 00 timer 217 tmc01 timer control register 01 timer 219 tmc10 timer control register 10 timer 217 tmc11 timer control register 11 timer 217 tmc2 timer mode control register 2 timer 244 tmc3 timer mode control register 3 timer 244 tmc4 timer mode control register 4 timer 244 tmc5 timer mode control register 5 timer 244 tmic2 interrupt control register intc 441 tmic3 interrupt control register intc 441 tmic4 interrupt control register intc 441 tmic5 interrupt control register intc 441 txb0 transmit buffer register 0 uart 309 txb1 transmit buffer register 1 uart 309 vswc system wait control register bcu 87 wdcs watchdog timer clock se lection register wdt 272 wdtic interrupt control register intc 441 wdtm watchdog timer mode register wdt 273, 444 week week count register rtc 265 weekb week count setting register rtc 265 user?s manual u15905ej2v1ud 543 appendix b instruction set list b.1 conventions (1) symbols used to describe operands symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used main ly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the remainders of division result s and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the condition codes sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) symbols used to describe opcodes symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list appendix b instruction set list user?s manual u15905ej2v1ud 544 (3) symbols used in operations symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) half-word halfword (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) symbols used in execution clock symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency). appendix b instruction set list user?s manual u15905ej2v1ud 545 (5) symbols used in flag operations symbol explanation (blank) no change 0 clear to 0 set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z 0 0 1 0 z = 1 zero nz 1 0 1 0 z = 0 not zero nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) s/n 0 1 0 0 s = 1 negative ns/p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed appendix b instruction set list user?s manual u15905ej2v1ud 546 b.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 rrrrr010010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,half-word)) 4 4 4 bit#3, disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extend(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 rrrrr010011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r appendix b instruction set list user?s manual u15905ej2v1ud 547 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (returned pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 3 3 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12[reg1] 0000011001iiiiil lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 2 2 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr ddddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11 appendix b instruction set list user?s manual u15905ej2v1ud 548 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,half-word)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,half-word) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 rrrrr010000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 rrrrr010111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 r rrr r gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3 appendix b instruction set list user?s manual u15905ej2v1ud 549 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp ? 4 repeat 1 step above until all regs in list12 is stored sp sp ? zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5)) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16)) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 appendix b instruction set list user?s manual u15905ej2v1ud 550 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,half-word)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,half- word)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],half-word) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], half-word) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1 appendix b instruction set list user?s manual u15905ej2v1ud 551 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr[reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,half-word))) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend(gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend(gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (return pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 3 3 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the num ber of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states). appendix b instruction set list user?s manual u15905ej2v1ud 552 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. user?s manual u15905ej2v1ud 553 appendix c revision history c.1 major revisions in this edition page description throughout addition of products ( pd703200 and 703200y) throughout modification of minimum instruction execution time throughout deletion of backup mode p.20 change of pin names from v ddbu and v ssbu to v dd and v ss respectively in 1.5 pin configuration p.84 modification of 3.4.8 (1) setting data to special registers p.87 addition of 3.4.9 (2) access to special internal peripheral i/o registers p.165 modification of figure 4-32 block diagram of pdh0 to pdh7 p.178 modification of 5.2.1 pin status when internal rom, internal ram, or internal peripheral i/o is accessed p.196 modification of 5.11 bus timing p.268 modification of 9.3.4 notes p.283 modification of tables 11-2 and 11-3 example of setting a/d conversion time p.289 addition of 11.5 notes on use p.290 addition of 11.6 how to read a/d converter characteristics table p.331 modification of 13.7 cautions p.422 modification of 16.11 precautions p.440 addition of caution to 17.3.4 interrupt control register (xxicn) p.443 addition of caution to 17.3.6 in-service priority register (ispr) p.453 addition of 17.6.2 debug trap p.482 addition of 21.2 functional overview p.484 addition of figure 21-1 wiring example of v850es/sa2 flash write adapter (fa-100gc-8eu-a) p.485 addition of table 21-4 wiring of v850es/sa2 flash write adapter (fa-100gc-8eu-a) p.486 addition of figure 21-2 wiring example of v850es/sa3 flash write adapter (fa-121f1-ea6-a) p.487 addition of table 21-5 wiring of v850es/sa3 flash write adapter (fa-121f1-ea6-a) p.491 addition of 21.5.2 flmd1 pin p.499 addition of 21.7 rewriting by self programming p.503 modification of chapter 22 electrical specifications p.532 addition of 100-pin plasti c tqfp (fine pitch) to chapter 23 package drawings p.534 addition of chapter 24 recommended soldering conditions p.536 addition of appendix a register index p.543 addition of appendix b instruction set list p.553 addition of appendix c revision history major revisions in modifica tion version (u15905ej2v1ud00) p.19 modification of 1.4 ordering information p.534 modification of chapter 24 recommended soldering conditions |
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